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Author SHA1 Message Date
Linus Torvalds
3ceff4ea07 sound updates for 5.17-rc1
It's a relatively calm development cycle, but still lots of updates in
 the driver side like Intel SOF.  Below are some highlights:
 
 * ALSA / ASoC core:
 - A new kselftest for ALSA control API
 - PCM NO_REWINDS support
 - Potential race fixes around control removals
 - Unify x86 SG-buffer memory allocation code
 - Cleanups and race fixes for ASoC DPCM locking
 
 * ASoC:
 - Refinements and cleanups around the delay() APIs
 - Wider use of dev_err_probe().
 - Continuing cleanups and improvements to the SOF code
 - Support for pin switches in simple-card derived cards
 - Support for AMD Renoir ACP, Asahi Kasei Microdevices AKM4375, Intel
   systems using NAU8825 and MAX98390, Mediatek MT8915, nVidia Tegra20
   S/PDIF, Qualcomm systems using ALC5682I-VS and Texas Instruments
   TLV320ADC3xxx
 
 * HD-audio / USB-audio:
 - Fix deadlock at HD-audio codec unbinding
 - Fixes for Tegra194 HD-audio, new HDA support for CS35L41 codec
 - Quirks for Lenovo and HP machines, Gigabyte mobo, Bose device
 
 * Misc:
 - Fix virmidi drain behavior
 
 Note that the merge of CS35L41 codec support is still half-baked, and
 at least one ACPI change is missing.  Although this won't hinder the
 kernel build itself, we're going to catch up before RC1.
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Merge tag 'sound-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound updates from Takashi Iwai:
 "It's a relatively calm development cycle, but still lots of updates in
  the driver side like Intel SOF. Below are some highlights:

  ALSA / ASoC core:
   - A new kselftest for ALSA control API
   - PCM NO_REWINDS support
   - Potential race fixes around control removals
   - Unify x86 SG-buffer memory allocation code
   - Cleanups and race fixes for ASoC DPCM locking

  ASoC:
   - Refinements and cleanups around the delay() APIs
   - Wider use of dev_err_probe().
   - Continuing cleanups and improvements to the SOF code
   - Support for pin switches in simple-card derived cards
   - Support for AMD Renoir ACP, Asahi Kasei Microdevices AKM4375, Intel
     systems using NAU8825 and MAX98390, Mediatek MT8915, nVidia Tegra20
     S/PDIF, Qualcomm systems using ALC5682I-VS and Texas Instruments
     TLV320ADC3xxx

  HD-audio / USB-audio:
   - Fix deadlock at HD-audio codec unbinding
   - Fixes for Tegra194 HD-audio, new HDA support for CS35L41 codec
   - Quirks for Lenovo and HP machines, Gigabyte mobo, Bose device

  Misc:
   - Fix virmidi drain behavior

  Note that the merge of CS35L41 codec support is still half-baked, and
  at least one ACPI change is missing. Although this won't hinder the
  kernel build itself, we're going to catch up before RC1"

* tag 'sound-5.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (415 commits)
  ALSA: hda: intel-dsp-config: reorder the config table
  ALSA: hda: intel-dsp-config: add JasperLake support
  ALSA: hda: cs35l41: fix double free on error in probe()
  ALSA: hda: Fix dependencies of CS35L41 on SPI/I2C buses
  ALSA: hda: Fix dependency on ASoC cs35l41 codec
  ASoC: cs35l41: Add support for hibernate memory retention mode
  ASoC: cs35l41: Update handling of test key registers
  ALSA: intel_hdmi: Check for error num after setting mask
  ASoC: wcd9335: Keep a RX port value for each SLIM RX mux
  ASoC: amd: acp: acp-mach: Change default RT1019 amp dev id
  ALSA: virmidi: Remove duplicated code
  ALSA: seq: virmidi: Add a drain operation
  ASoC: topology: Fix typo
  ASoC: fsl_asrc: refine the check of available clock divider
  ASoC: Intel: bytcr_rt5640: Add support for external GPIO jack-detect
  ASoC: Intel: bytcr_rt5640: Support retrieving the codec IRQ from the AMCR0F28 ACPI dev
  ASoC: rt5640: Add support for boards with an external jack-detect GPIO
  ASoC: rt5640: Allow snd_soc_component_set_jack() to override the codec IRQ
  ASoC: rt5640: Change jack_work to a delayed_work
  ASoC: rt5640: Fix possible NULL pointer deref on resume
  ...
2022-01-14 14:55:38 +01:00
Sameer Pujar
146b3a77af arm64: tegra: Remove non existent Tegra194 reset
Tegra194 does not really have "hda2codec_2x" related reset. Hence drop
this entry to reflect actual HW.

Fixes: 4878cc0c9f ("arm64: tegra: Add HDA controller on Tegra194")
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Link: https://lore.kernel.org/r/1640260431-11613-4-git-send-email-spujar@nvidia.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2022-01-01 16:46:37 +01:00
Thierry Reding
914ed1f565 arm64: tegra: Add host1x hotflush reset on Tegra210
Add the host1x memory client hotflush reset on Tegra210.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-17 14:58:58 +01:00
Thierry Reding
6de481e5ab arm64: tegra: Hook up MMC and BPMP to memory controller
Use the interconnects property to hook up the MMC and BPMP to the memory
controller. This is needed to set the correct bus-level DMA mask, which
is a prerequisite for adding IOMMU support.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:03 +01:00
Thierry Reding
eed280dfe9 arm64: tegra: Add memory controller on Tegra234
This adds the memory controller and the embedded external memory
controller found on the Tegra234 SoC.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:03 +01:00
Thierry Reding
cc9396676c arm64: tegra: Add EMC general interrupt on Tegra194
Add the missing EMC general interrupt for the external memory controller
on Tegra194.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:03 +01:00
Prathamesh Shete
c2fee44399 arm64: tegra: Update SDMMC4 speeds for Tegra194
Add required device-tree properties to populate all speed
modes supported by SDMMC4 instance of Tegra194 SDHCI controller.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Jon Hunter
a52280c844 arm64: tegra: Add dma-coherent for Tegra194 VIC
DMA operations for the Tegra194 Video Image Compositor (VIC) are
coherent and so populate the 'dma-coherent' property.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
553f07360e arm64: tegra: Rename Ethernet PHY nodes
Name the Ethernet PHY device tree nodes as expected by the DT schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
0275294736 arm64: tegra: Remove unused only-1-8-v properties
The only-1-8-v property is not support by an DT schema, so drop it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
f2ef6a9180 arm64: tegra: Sort Tegra210 XUSB clocks correctly
Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
28a44b900e arm64: tegra: Add missing TSEC properties on Tegra210
Add missing interrupts, clocks, clock-names, reset and reset-names
properties for the TSEC blocks found on Tegra210.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
9c1b3ef8e2 arm64: tegra: jetson-nano: Remove extra PLL power supplies for PCIe and XUSB
The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB controller device
tree nodes.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
54215999f3 arm64: tegra: smaug: Remove extra PLL power supplies for XUSB
The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the XUSB controller device tree
node.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
31bc882c03 arm64: tegra: jetson-tx1: Remove extra PLL power supplies for PCIe and XUSB
The XUSB pad controller handles the various PLL power supplies, so
remove any references to them from the PCIe and XUSB controller device
tree nodes.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
635fb5d4cb arm64: tegra: Rename GPIO hog nodes to match schema
GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to
the DT schema. Rename all such nodes to allow validation to pass.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
1dcf00ae82 arm64: tegra: Remove unsupported regulator properties
Remove the unsupported "regulator-disable-ramp-delay" properties which
ended up in various DTS files for some reason.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
99d9bde5b4 arm64: tegra: Rename TCU node to "serial"
The TCU is basically a serial port (albeit a fancy one), so it should be
named "serial".

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
c453cc9e9e arm64: tegra: Remove undocumented Tegra194 PCIe "core_m" clock
The "core_m" clock is not documented in the Tegra194 PCIe device tree
bindings, so remove it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
1ff7505907 arm64: tegra: Drop unused properties for Tegra194 PCIe
The num-viewport property is never used and can be dropped, whereas the
"iommus" property is not needed since we use "iommu-map-mask" and
"iommu-map" already.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
cd6157c197 arm64: tegra: Fix Tegra194 HSP compatible string
The HSP instances on Tegra194 are not fully compatible with the version
found on Tegra186, so drop the fallback compatible string from the list.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
2fcb87970e arm64: tegra: Drop unsupported nvidia,lpdr property
The Tegra194 pinmux DT bindings do not define the nvidia,lpdr property,
so drop them from the device trees that have listed them.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
56797e6259 arm64: tegra: Use JEDEC vendor prefix for SPI NOR flash chips
The standard "jedec," vendor prefix should be used for SPI NOR flash
chips. This allows the right DT schema to be picked for validation.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
e7445ab7dc arm64: tegra: Drop unit-address for audio card graph endpoints
Audio graph endpoints don't have a "reg" property, so they shouldn't
have a unit-address either.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
2b14cbd643 arm64: tegra: Adjust length of CCPLEX cluster MMIO region
The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4
MiB - 1. This was likely presumed to be the "limit" rather than length.
Fix it up.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
548c9c5aaf arm64: tegra: Fix Tegra186 compatible string list
The I2C controller found on Tegra186 is not fully compatible with the
Tegra210 version, so drop the fallback compatible string from the list.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:02 +01:00
Thierry Reding
4b5ae31fb7 arm64: tegra: Rename power-monitor input nodes
Child nodes of the TI INA3221 power monitor device tree node should be
called input@* according to the DT schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
fe57ff5365 arm64: tegra: Rename thermal zones nodes
The DT schema requires that nodes representing thermal zones include a
"-thermal" suffix in their name.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
fce5d07316 arm64: tegra: Sort Tegra132 XUSB clocks correctly
Make the order of the clocks and clock-names properties match the order
in the device tree bindings. This isn't strictly necessary from a point
of view of the operating system because matching will be done based on
the clock-names, but it makes it easier to validate the device trees
against the DT schema.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
9f27a6c421 arm64: tegra: Drop unused AHCI clocks on Tegra132
The CML1 and PLL_E clocks are never explicitly used by the AHCI
controller found on Tegra132, so drop them from the corresponding device
tree node.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
92564257d7 arm64: tegra: Fix Tegra132 I2C compatible string list
The I2C controller found on Tegra124 is not fully compatible with the
Tegra114 version, so drop the fallback compatible string from the list.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
ed9e9a6eb1 arm64: tegra: Add OPP tables on Tegra132
Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the
EMC. While at it, add the missing "#interconnect-cells" properties to
the memory controller and external memory controller nodes. Also set the
"#reset-cells" property for the memory controller because it exports the
hotflush reset controls.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
bb43b219c8 arm64: tegra: Fix compatible string for Tegra132 timer
The TKE (time-keeping engine) found on Tegra132 is not backwards
compatible with the version found on Tegra20, so update the compatible
string list accordingly.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
64b4078276 arm64: tegra: Remove unsupported properties on Norrin
The Tegra PMC device tree bindings don't support the "#wake-cells" and
"nvidia,reset-gpio" properties, so remove them.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
2c6fd24dcb arm64: tegra: Fix unit-addresses on Norrin
The AS3722 pinmux device tree node doesn't have a "reg" property and
therefore must not have a unit-address, so drop it.

While at it, add missing unit-addresses for the charger and smart
battery IC's on the ChromeOS embedded controller's I2C tunnel bus.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
bd1fefcbdd arm64: tegra: Add native timer support on Tegra186
The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tree node on Tegra186.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
097e01c610 arm64: tegra: Rename top-level regulators
Regulators defined at the top level in device tree are no longer part of
a simple bus and therefore don't have a reg property. Nodes without a
reg property shouldn't have a unit-address either, so drop the unit
address from the node names. To ensure nodes aren't duplicated (in which
case they would end up merged in the final DTB), append the name of the
regulator to the node name.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
4cc3e3e164 arm64: tegra: Rename top-level clocks
Clocks defined at the top level in device tree are no longer part of a
simple bus and therefore don't have a reg property. Nodes without a reg
property shouldn't have a unit-address either, so drop the unit address
from the node names. To ensure nodes aren't duplicated (in which case
they would end up merged in the final DTB), append the name of the clock
to the node name.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Jon Hunter
e762232f94 arm64: tegra: Add ISO SMMU controller for Tegra194
The display controllers are attached to a separate ARM SMMU instance
that is dedicated to servicing isochronous memory clients. Add this ISO
instance of the ARM SMMU to device tree.

Please note that the display controllers are not hooked up to this SMMU
yet, because we are still missing a means to transition framebuffers
used by the bootloader to the kernel.

This based upon an initial patch by Thierry Reding <treding@nvidia.com>.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Jon Hunter
f7eb278572 arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194
Populate the device-tree nodes for NVENC and NVJPG Host1x engines on
Tegra186 and Tegra194.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Prathamesh Shete
ff21087e61 arm64: tegra: Add support to enumerate SD in UHS mode
Add support to enumerate SD in UHS mode on Tegra194. Add required
device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic
pad voltage switching and enumerate SD card in UHS-I modes.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Mikko Perttunen
533337d5c8 arm64: tegra: Add NVIDIA Jetson AGX Orin Developer Kit support
The Jetson AGX Orin Developer Kit is a continuation of the Jetson
Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
a12cf5c339 arm64: tegra: Describe Tegra234 CPU hierarchy
The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each,
for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches
with each cluster having an additional 256 KiB unified L2 cache and a 2
MiB L3 cache.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Thierry Reding
f0e1266818 arm64: tegra: Add main and AON GPIO controllers on Tegra234
These two controllers expose general purpose I/O pins that can be used
to control or monitor a variety of signals.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Mikko Perttunen
06ad2ec4e5 arm64: tegra: Add Tegra234 TCU device
Add a device for TCU (Tegra Combined UART) used for serial console.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:01 +01:00
Mikko Perttunen
e086d82d4f arm64: tegra: Fill in properties for Tegra234 eMMC
Add missing properties to the eMMC controller, as required to use it on
actual hardware.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:00 +01:00
Mikko Perttunen
98094be152 arm64: tegra: Update Tegra234 BPMP channel addresses
On final Tegra234 systems, shared memory for communication with BPMP is
located at offset 0x70000 in SYSRAM.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:00 +01:00
Mikko Perttunen
e537adde13 arm64: tegra: Add clock for Tegra234 RTC
The RTC device requires a clock. Add it.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:00 +01:00
Thierry Reding
7fa307524a arm64: tegra: Fixup SYSRAM references
The json-schema bindings for SRAM expect the nodes to be called "sram"
rather than "sysram" or "shmem". Furthermore, place the brackets around
the SYSRAM references such that a two-element array is created rather
than a two-element array nested in a single-element array. This is not
relevant for device tree itself, but allows the nodes to be properly
validated against json-schema bindings.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16 16:51:00 +01:00
Mauro Carvalho Chehab
b9e2404c8b arm64: tegra: Fix pcie-ep DT nodes
As defined by Documentation/devicetree/bindings/pci/pci-ep.yaml,
PCIe endpoints match this pattern:

	properties:
	  $nodename:
	    pattern: "^pcie-ep@"

Change the existing ones in order to avoid those warnings:

	arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml: pcie_ep@14160000: $nodename:0: 'pcie_ep@14160000' does not match '^pcie-ep@'
		From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
	arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml: pcie_ep@14180000: $nodename:0: 'pcie_ep@14180000' does not match '^pcie-ep@'
		From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
	arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml: pcie_ep@141a0000: $nodename:0: 'pcie_ep@141a0000' does not match '^pcie-ep@'
		From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
	arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml: pcie_ep@14160000: $nodename:0: 'pcie_ep@14160000' does not match '^pcie-ep@'
		From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
	arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml: pcie_ep@14180000: $nodename:0: 'pcie_ep@14180000' does not match '^pcie-ep@'
		From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
	arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml: pcie_ep@141a0000: $nodename:0: 'pcie_ep@141a0000' does not match '^pcie-ep@'
		From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
	arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml: pcie_ep@14160000: $nodename:0: 'pcie_ep@14160000' does not match '^pcie-ep@'
		From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
	arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml: pcie_ep@14180000: $nodename:0: 'pcie_ep@14180000' does not match '^pcie-ep@'
		From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
	arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml: pcie_ep@141a0000: $nodename:0: 'pcie_ep@141a0000' does not match '^pcie-ep@'
		From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-07 21:23:37 +02:00