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Nishanth Menon
a172c86931 arm64: dts: ti: k3-j7200: Correct the d-cache-sets info
A72 Cluster (chapter 1.3.1 [1]) has 48KB Icache, 32KB Dcache and 1MB L2 Cache
 - ICache is 3-way set-associative
 - Dcache is 2-way set-associative
 - Line size are 64bytes

32KB (Dcache)/64 (fixed line length of 64 bytes) = 512 ways
512 ways / 2 (Dcache is 2-way per set) = 256 sets.

So, correct the d-cache-sets info.

[1] https://www.ti.com/lit/pdf/spruiu1

Fixes: d361ed8845 ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211113042640.30955-1-nm@ti.com
2021-12-03 17:21:36 +05:30
Nishanth Menon
e9ba3a5bc6 arm64: dts: ti: k3-j721e: Fix the L2 cache sets
A72's L2 cache[1] on J721e[2] is 1MB. A72's L2 is fixed line length of
64 bytes and 16-way set-associative cache structure.

1MB of L2 / 64 (line length) = 16384 ways
16384 ways / 16 = 1024 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
[2] http://www.ti.com/lit/pdf/spruil1

Fixes: 2d87061e70 ("arm64: dts: ti: Add Support for J721E SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211113043639.4413-1-nm@ti.com
2021-12-03 17:19:55 +05:30
Nishanth Menon
d0c826106f arm64: dts: ti: k3-j7200: Fix the L2 cache sets
A72's L2 cache[1] on J7200[2] is 1MB. A72's L2 is fixed line length of
64 bytes and 16-way set-associative cache structure.

1MB of L2 / 64 (line length) = 16384 ways
16384 ways / 16 = 1024 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
[2] https://www.ti.com/lit/pdf/spruiu1

Fixes: d361ed8845 ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211113043638.4358-1-nm@ti.com
2021-12-03 17:19:04 +05:30
Nishanth Menon
a27a93bf70 arm64: dts: ti: k3-am642: Fix the L2 cache sets
A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length
of 64 bytes and 16-way set-associative cache structure.

256KB of L2 / 64 (line length) = 4096 ways
4096 ways / 16 = 256 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en
[2] https://www.ti.com/lit/pdf/spruim2

Fixes: 8abae9389b ("arm64: dts: ti: Add support for AM642 SoC")
Reported-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211113043635.4296-1-nm@ti.com
2021-12-03 17:18:37 +05:30
Kishon Vijay Abraham I
3f92a5be60 arm64: dts: ti: j721e-main: Fix 'dtbs_check' in serdes_ln_ctrl node
Fix 'dtbs_check' in serdes_ln_ctrl (mux@4080) node by changing the node
name to mux-controller@4080.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211126084555.17797-3-kishon@ti.com
2021-12-03 17:16:19 +05:30
Kishon Vijay Abraham I
4d39849063 arm64: dts: ti: j7200-main: Fix 'dtbs_check' serdes_ln_ctrl node
Fix 'dtbs_check' in serdes_ln_ctrl (serdes-ln-ctrl@4080) node by
changing the node name to mux-controller@4080.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211126084555.17797-2-kishon@ti.com
2021-12-03 17:16:19 +05:30
Jernej Skrabec
a8a051984a
arm64: dts: allwinner: h6: tanix-tx6: Enable bluetooth
Tanix TX6 comes either with RTL8822BS or RTL8822CS wifi+bt combo module.
Wifi part is already enabled in tanix DTSI. Let's enable also bluetooth.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2021-12-03 10:55:13 +01:00
Jernej Skrabec
0835819309
arm64: dts: allwinner: h6: tanix: Add MMC1 node
Both, Tanix TX6 and Tanix TX6 mini, have SDIO wifi module, albeit
different. However, driver can be autoprobed via SDIO ID.

Add MMC1 node, so kernel can discover wifi module and load driver for
it.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2021-12-03 10:55:13 +01:00
Jernej Skrabec
fa33ec5157
arm64: dts: allwinner: h6: Add Tanix TX6 mini dts
Tanix TX6 mini is less capable version of Tanix TX6 although it comes
with some features not present on Tanix TX6.

Basic specs:
- H6 SoC
- 2 GiB DDR3 RAM
- HDMI
- SPDIF
- 2x USB
- analogue audio
- CVBS
- SD card
- IR remote
- LED display
- fast ethernet
- XR819 wifi
- 16 GiB eMMC

Currently supported features doesn't differ that much from Tanix TX6,
but that will change soon.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2021-12-03 10:55:13 +01:00
Jernej Skrabec
8ff8d6936e
arm64: dts: allwinner: h6: tanix-tx6: Split to DT and DTSI
There is another very similar device to Tanix TX6, namely Tanix TX6
mini. Because most of the board design is shared, it makes sense to have
common nodes in DTSI file.

Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2021-12-03 10:55:13 +01:00
Janne Grunau
c03edf1c0f arm64: dts: apple: t8103: Add cd321x nodes
All M1 Mac devices have 2 SoC connected USB-C ports and use cd321x USB
type C port switch and power deliver controllers. I2c bus and addresses
configuration are for all devices equal.
The iMac (24-inch, 2021) has a configuration with 2 additional USB-C
ports (j456) using two additional cd321x controllers.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Tested-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-01 23:21:35 +09:00
Janne Grunau
90458f6eec arm64: dts: apple: t8103: Add i2c nodes
Apple M1 has at least 5 i2c controllers. i2c0, i2c1 and i2c3 are used
on all M1 Mac devices. The 2020 Mac Mini uses i2c2 and the 13-inch
MacBook Pro uses i2c2 and i2c4.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Tested-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-01 23:21:33 +09:00
Janne Grunau
7c77ab91b3 arm64: dts: apple: Add missing M1 (t8103) devices
This adds support for following Apple M1 devices:
 - MacBook Pro (13-inch, M1, 2020)
 - MacBook Air (M1, 2020)
 - iMac (24-inch 2021)

Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Tested-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-01 23:21:30 +09:00
Janne Grunau
0668639eaf arm64: dts: apple: add #interrupt-cells property to pinctrl nodes
Required for devices trying to use pinctrl devices as interrupt
controller.

Fixes: 0a8282b831 ("arm64: apple: Add pinctrl nodes")
Signed-off-by: Janne Grunau <j@jannau.net>
Cc: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Sven Peter <sven@svenpeter.dev>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Tested-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-01 23:11:45 +09:00
Sin Hui Kho
8dce88fe80 arm64: dts: Update NAND MTD partition for Agilex and Stratix 10
Change NAND flash MTD partition in device tree after implementation of
UBI and UBIFS. "u-boot" partition remain for raw u-boot image, but "root"
partition is use for UBI image containing all other components.

Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-12-01 08:07:41 -06:00
Jerome Brunet
0a62b3cc0a arm64: dts: meson: p241: add sound support
Add the p241 sound card support. This board can play audio through HDMI
and the internal DAC.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20211130100159.214489-3-jbrunet@baylibre.com
2021-12-01 10:27:13 +01:00
Jerome Brunet
75fb3b1be5 arm64: dts: meson: p241: add vcc_5v regulator
Add the VCC_5V regulator, which feeds the HDMI, USB and audio amplifier.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20211130100159.214489-2-jbrunet@baylibre.com
2021-12-01 10:27:13 +01:00
Vyacheslav Bocharov
c2584017f7 arm64: meson: fix dts for JetHub D1
Fix misplace of cpu_cooling_maps for JetHub D1, move it to right place.

Fixes: 8e279fb290 ("arm64: dts: meson-axg: add support for JetHub D1")
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20211125130246.1086627-1-adeep@lexina.in
2021-12-01 10:25:38 +01:00
Dmitry Baryshkov
b0293c19d4 arm64: dts: qcom: msm8916: fix MMC controller aliases
Change sdhcN aliases to mmcN to make them actually work. Currently the
board uses non-standard aliases sdhcN, which do not work, resulting in
mmc0 and mmc1 hosts randomly changing indices between boots.

Fixes: c4da5a5616 ("arm64: dts: qcom: Add msm8916 sdhci configuration nodes")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211201020559.1611890-1-dmitry.baryshkov@linaro.org
2021-11-30 22:06:35 -06:00
Martin Botka
556a9f3ae1 arm64: dts: qcom: sm6125: Add power domains to sdhc
Add RPM Power Domains to internal eMMC and SDCard.

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211130212332.25401-4-martin.botka@somainline.org
2021-11-30 22:06:34 -06:00
Martin Botka
d0bfc92303 arm64: dts: qcom: sm6125: Add RPMPD node
Add RPM Power Distribution node for sm6125 SoC.

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211130212332.25401-3-martin.botka@somainline.org
2021-11-30 22:06:34 -06:00
Kshitiz Godara
3ebf11fa4a arm64: dts: qcom: sc7280-crd: Add Touchscreen and touchpad support
Add Touchscreen and touchpad hid-over-i2c node for the sc7280 CRD board

Signed-off-by: Kshitiz Godara <kgodara1@codeaurora.org>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1638185497-26477-5-git-send-email-quic_rjendra@quicinc.com
2021-11-30 22:06:34 -06:00
Kshitiz Godara
248da168fb arm64: dts: qcom: sc7280: Define EC and H1 nodes for IDP/CRD
The IDP2 and CRD boards share the EC and H1 parts, so define
all related device nodes into a common file and include them
in the idp2 and crd dts files to avoid duplication.

Signed-off-by: Kshitiz Godara <kgodara@codeaurora.org>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1638185497-26477-4-git-send-email-quic_rjendra@quicinc.com
2021-11-30 22:06:34 -06:00
Rajendra Nayak
427b249504 arm64: dts: qcom: sc7280-crd: Add device tree files for CRD
CRD (Compute Reference Design) is a sc7280 based board, largely
derived from the existing IDP board design with some key deltas
1. has EC and H1 over SPI similar to IDP2
2. touchscreen and trackpad support
3. eDP display

We just add the barebones dts file here, subsequent patches will
add support for EC/H1 and other components.

Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Tested-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1638185497-26477-3-git-send-email-quic_rjendra@quicinc.com
2021-11-30 22:06:34 -06:00
Dang Huynh
95dcb99777 arm64: dts: qcom: Drop input-name property
This property doesn't seem to exist in the documentation nor
in source code, but for some reason it is defined in a bunch
of device trees.

Signed-off-by: Dang Huynh <danct12@riseup.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211123162436.1507341-1-danct12@riseup.net
2021-11-30 22:06:34 -06:00
Dang Huynh
6867430332 arm64: dts: qcom: sdm660-xiaomi-lavender: Add volume up button
This enables the volume up key.

Signed-off-by: Dang Huynh <danct12@riseup.net>
Tested-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211121170449.1124048-1-danct12@riseup.net
2021-11-30 21:06:56 -06:00
Stephan Gerhold
1c0ac047bb arm64: dts: qcom: msm8916: Add RPM sleep stats
MSM8916 is similar to the other SoCs that had the RPM stats node added
in commit 290bc68465 ("arm64: dts: qcom: Enable RPM Sleep stats").
However, the dynamic offset readable at 0x14 seems only available on
some of the newer firmware versions. To be absolutely sure, make use
of the new qcom,msm8916-rpm-stats compatible that reads the sleep stats
from a fixed offset of 0xdba0.

Statistics are available for a "vmin" and "xosd" low power mode:

$ cat /sys/kernel/debug/qcom_stats/vmin
Count: 0
Last Entered At: 0
Last Exited At: 0
Accumulated Duration: 0
Client Votes: 0x0
$ cat /sys/kernel/debug/qcom_stats/xosd
Count: 0
Last Entered At: 0
Last Exited At: 0
Accumulated Duration: 0
Client Votes: 0x0

Cc: Maulik Shah <mkshah@codeaurora.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211119213953.31970-4-stephan@gerhold.net
2021-11-30 21:03:35 -06:00
Thara Gopinath
8e0e8016cb arm64: dts: qcom: sm8250: Add CPU opp tables
Add OPP tables to scale DDR and L3 with CPUs for SM8250 SoCs.

Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211110215330.74257-1-thara.gopinath@linaro.org
2021-11-30 21:00:19 -06:00
Dinh Nguyen
f4c35356e0 arm64: dts: n5x: add qspi, usb, and ethernet support
Populate the N5X board dts file with support for QSPI, USB, and
ethernet.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2021-11-30 14:10:44 -06:00
Kieran Bingham
cdda01947b arm64: dts: renesas: r8a779a0: Add DU support
Provide the device nodes for the DU on the V3U platforms.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Link: https://lore.kernel.org/r/20211126095445.932930-2-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26 14:08:20 +01:00
Kieran Bingham
bd4fa23731 arm64: dts: renesas: salvator-common: Merge hdmi0_con
The remote endpoint for the hdmi connector is specfied through a
reference to the hdmi0_con endpoint, which is in the same file.

Simplify by specifying the remote-endpoint directly in the hdmi0_con
endpoint.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20211124152815.3926961-3-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26 14:08:20 +01:00
Kieran Bingham
9fd8bbefc3 arm64: dts: renesas: ulcb: Merge hdmi0_con
The remote endpoint for the hdmi connector is specfied through a
reference to the hdmi0_con endpoint, which is in the same file.

Simplify by specifying the remote-endpoint directly in the hdmi0_con
endpoint.

Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20211124152815.3926961-2-kieran.bingham+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26 14:08:20 +01:00
Biju Das
36959e2108 arm64: dts: renesas: r9a07g044: Add OPP table
Add OPP table for RZ/G2L SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211124154316.28365-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26 14:08:20 +01:00
Geert Uytterhoeven
7744b393c9 arm64: dts: renesas: Fix operating point table node names
Align the node names of device nodes representing operating point v2
tables with the expectations of the DT bindings in
Documentation/devicetree/bindings/opp/opp-v2.yaml.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/ac885456ffb00fa4cc4069b9967761df2c98c3d8.1637764588.git.geert+renesas@glider.be
2021-11-26 14:08:20 +01:00
Biju Das
44c2d2c2d2 arm64: dts: renesas: rzg2l-smarc-som: Enable watchdog
Enable watchdog{0, 1, 2} interfaces on RZ/G2L SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211123141420.23529-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26 14:08:20 +01:00
Biju Das
eb7621ce33 arm64: dts: renesas: r9a07g044: Add WDT nodes
Add WDT{0, 1, 2} nodes to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211123141420.23529-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26 14:08:20 +01:00
Biju Das
fee3eae133 arm64: dts: renesas: r9a07g044: Rename SDHI clocks
Rename the below SDHI clocks to match with the clocks used in driver.

     imclk->core
     clk_hs->clkh
     imclk2->cd

Also re-arrange the clocks to match with the sorting order used in the
binding document.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20211122103905.14439-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26 14:08:19 +01:00
Lad Prabhakar
c81bd70f47 arm64: dts: renesas: rzg2l-smarc-som: Enable serial NOR flash
Enable mt25qu512a flash connected to QSPI0.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20211121234906.9602-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26 14:08:19 +01:00
Biju Das
00d071e23c arm64: dts: renesas: rzg2l-smarc-som: Enable OSTM
Enable OSTM{1, 2} interfaces on RZ/G2L SMARC EVK.
OSTM0 is reserved for TF-A.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211118191826.2026-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26 14:08:19 +01:00
Biju Das
59a7d68b69 arm64: dts: renesas: r9a07g044: Add OSTM nodes
Add OSTM{0,1,2} nodes to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211118191826.2026-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26 14:08:19 +01:00
Biju Das
5fcf8b0656 arm64: dts: renesas: r9a07g044: Sort psci node
Sort psci node alphabetically.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211112081003.15453-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26 14:08:19 +01:00
Peng Fan
7a0df1f969 arm64: dts: ti: k3-j721e: correct cache-sets info
A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache
 - ICache is 3-way set-associative
 - Dcache is 2-way set-associative
 - Line size are 64bytes

So correct the cache-sets info.

Fixes: 2d87061e70 ("arm64: dts: ti: Add Support for J721E SoC")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211112063155.3485777-1-peng.fan@oss.nxp.com
2021-11-26 18:02:27 +05:30
Janne Grunau
8979ead988 arm64: dts: apple: change ethernet0 device type to ethernet
Fixes make dtbs_check errors for t8103-j274.dts due to missing pci
properties.

Fixes: e1bebf9781 ("arm64: dts: apple: j274: Expose PCI node for the Ethernet MAC address")
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Tested-by: Hector Martin <marcan@marcan.st>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-11-26 15:41:21 +09:00
Chanho Park
5fe762515b
arm64: dts: exynos: drop samsung,ufs-shareability-reg-offset in ExynosAutov9
samsung,ufs-shareability-reg-offset is not necessary anymore since it
was integrated into the second argument of samsung,sysreg.

Fixes: 31bbac5263 ("arm64: dts: exynos: add initial support for exynosautov9 SoC")
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20211102064826.15796-1-chanho61.park@samsung.com
Link: https://lore.kernel.org/r/20211124085042.9649-2-krzysztof.kozlowski@canonical.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-11-25 14:46:00 +01:00
Mathew McBride
c88c5e4619 arm64: dts: ten64: remove redundant interrupt declaration for gpio-keys
gpio-keys already 'inherits' the interrupts from the controller
of the specified GPIO, so having another declaration is redundant.
On >=v5.15 this started causing an oops under gpio_keys_probe as
the IRQ was already claimed.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
Fixes: 418962eea3 ("arm64: dts: add device tree for Traverse Ten64 (LS1088A)")
Cc: stable@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-23 20:25:34 +08:00
Samuel Holland
00b9773b12
arm64: dts: allwinner: a64: Update MBUS node
In order to support memory dynamic frequency scaling (MDFS), the MBUS
binding now requires enumerating more resources. Provide them in the
device tree.

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211118031841.42315-6-samuel@sholland.org
2021-11-23 11:29:56 +01:00
Samuel Holland
c8f7b50785
ARM: dts: sunxi: h3/h5: Update MBUS node
In order to support memory dynamic frequency scaling (MDFS), the MBUS
binding now requires enumerating more resources. Provide them in the
device tree.

Since the H3 and H5 have different clock divider limits, they need
separate compatibles.

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20211118031841.42315-5-samuel@sholland.org
2021-11-23 11:29:52 +01:00
Peng Fan
ebd922967f arm64: dts: imx8qxp: add cache info
i.MX8QXP A35 Cluster has 32KB Icache, 32KB Dcache and 512KB L2 Cache
 - Icache is 2-way set associative
 - Dcache is 4-way set associative
 - L2cache is 8-way set associative
 - Line size are 64bytes

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-23 17:26:09 +08:00
Peng Fan
b0b46118ed arm64: dts: imx8qm: add cache info
i.MX8QM A53 Cluster has 32KB Icache, 32KB Dcache and 1MB L2 Cache
  - Icache is 2-way set associative
  - Dcache is 4-way set associative
  - L2cache is 16-way set associative
  - Line size are 64bytes

A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache
 - ICache is 3-way set-associative
 - Dcache is 2-way set-associative
 - L2Cache is 16-way set-associative
 - Line size are 64bytes

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-23 17:26:06 +08:00
Peng Fan
cb551b5e3b arm64: dts: imx8m: add cache info
i.MX8M Family use A53 Cores and has 32KB ICache with 32KB DCache.
 - Icache is 2-way set associative
 - Dcache is 4-way set associative
 - L2cache is 16-way set associative
 - Line size are 64bytes

Except i.MX8MQ has 1MB L2 Cache, others has 512KB L2 Cache.

So add the cache info in device tree and let use could see that
from /sys/devices/system/cpu/cpu[x]/cache/

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2021-11-23 17:25:52 +08:00