Paul Hsieh f5fa54f45a drm/amd/display: watermark latencies is not enough on DCN31 ... [Why] The original latencies were causing underflow in some modes. Resolution: 2880x1620@60p when HDR enable [How] 1. Replace with the up-to-date watermark values based on new measurments 2. Correct the ddr_wm_table name to DDR5 on DCN31 Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org		2022-02-02 18:35:00 -05:00
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dce60	drm/amd/display: dc/clk_mgr: make function static	2020-09-17 21:21:40 -04:00
dce100	drm/amd/display: remove redundant assignment to variable dp_ref_clk_khz	2020-04-22 18:11:45 -04:00
dce110	drm/amd/display: correct asic type check V2	2020-10-27 12:01:16 -04:00
dce112	drm/amd/display: correct asic type check V2	2020-10-27 12:01:16 -04:00
dce120	drm/amd/display: Copy max_clks_by_state after dce_clk_mgr_construct	2019-07-18 14:18:09 -05:00
dcn10	drm/amd/display: fix function scopes	2021-12-13 16:34:26 -05:00
dcn20	drm/amd/display: Revert W/A for hard hangs on DCN20/DCN21	2022-01-14 18:06:45 -05:00
dcn21	drm/amd/display: Revert W/A for hard hangs on DCN20/DCN21	2022-01-14 18:06:45 -05:00
dcn30	drm/amd/display: implement dc_mode_memclk	2021-12-14 16:08:41 -05:00
dcn31	drm/amd/display: watermark latencies is not enough on DCN31	2022-02-02 18:35:00 -05:00
dcn201	drm/amd/display: fix function scopes	2021-12-13 16:34:26 -05:00
dcn301	drm/amd/display: Update watermark values for DCN301	2022-02-02 18:35:00 -05:00
clk_mgr.c	drm/amd/display: add else to avoid double destroy clk_mgr	2021-11-24 14:06:52 -05:00
Makefile	drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into DRM_AMD_DC_DCN	2021-10-04 15:23:02 -04:00