Eric Yang 966443b592 drm/amd/display: block modes that require read bw greater than 30% ... Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2017-09-26 18:08:39 -04:00
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hw	drm/amd/display: Add DC interface for custom CSC matrix	2017-09-26 18:08:26 -04:00
bw_fixed.h	drm/amd/dc: Add dc display driver (v2)	2017-09-26 17:01:32 -04:00
clock_source.h	drm/amd/display: HDMI YCbCr422 12bpc pixel format issue	2017-09-26 17:13:37 -04:00
compressor.h	drm/amd/display: Connect DC resource to FBC compressor	2017-09-26 18:08:24 -04:00
core_dc.h	drm/amd/display: Connect DC resource to FBC compressor	2017-09-26 18:08:24 -04:00
core_status.h	drm/amd/display: Continue with stream enable if DP link training fails.	2017-09-26 18:06:58 -04:00
core_types.h	drm/amd/display: redesign mpc	2017-09-26 18:07:57 -04:00
custom_float.h	drm/amd/display: Enable regamma 25 segments and use double buffer.	2017-09-26 17:14:18 -04:00
dc_link_ddc.h	drm/amd/display: Refactor edid read.	2017-09-26 17:22:17 -04:00
dc_link_dp.h	drm/amd/display: Fix for tile MST	2017-09-26 17:23:36 -04:00
dce_calcs.h	drm/amd/display: refactor bw related variable structure in val_ctx	2017-09-26 18:07:01 -04:00
dcn_calcs.h	drm/amd/display: block modes that require read bw greater than 30%	2017-09-26 18:08:39 -04:00
hw_sequencer.h	drm/amd/display: Add DC interface for custom CSC matrix	2017-09-26 18:08:26 -04:00
link_hwss.h	drm/amd/display: Fix link retraining hw sequence for auto test	2017-09-26 17:08:10 -04:00
reg_helper.h	drm/amd/display: clarify delay param for REG_WAIT	2017-09-26 18:06:38 -04:00
resource.h	drm/amd/display: enable diags compilation	2017-09-26 18:08:25 -04:00