df798d43b3
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch of unnecessary head scratching. Add aliases using the skl+ plane names. And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1 as we only ever have 0-2 sprites per pipe on those platforms. v2: Don't break icl_nv12_y_plane_mask() (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240517171208.21313-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
131 lines
2.4 KiB
C
131 lines
2.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __INTEL_DISPLAY_LIMITS_H__
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#define __INTEL_DISPLAY_LIMITS_H__
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/*
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* Keep the pipe enum values fixed: the code assumes that PIPE_A=0, the
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* rest have consecutive values and match the enum values of transcoders
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* with a 1:1 transcoder -> pipe mapping.
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*/
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enum pipe {
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INVALID_PIPE = -1,
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PIPE_A = 0,
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PIPE_B,
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PIPE_C,
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PIPE_D,
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_PIPE_EDP,
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I915_MAX_PIPES = _PIPE_EDP
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};
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enum transcoder {
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INVALID_TRANSCODER = -1,
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/*
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* The following transcoders have a 1:1 transcoder -> pipe mapping,
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* keep their values fixed: the code assumes that TRANSCODER_A=0, the
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* rest have consecutive values and match the enum values of the pipes
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* they map to.
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*/
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TRANSCODER_A = PIPE_A,
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TRANSCODER_B = PIPE_B,
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TRANSCODER_C = PIPE_C,
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TRANSCODER_D = PIPE_D,
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/*
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* The following transcoders can map to any pipe, their enum value
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* doesn't need to stay fixed.
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*/
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TRANSCODER_EDP,
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TRANSCODER_DSI_0,
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TRANSCODER_DSI_1,
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TRANSCODER_DSI_A = TRANSCODER_DSI_0, /* legacy DSI */
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TRANSCODER_DSI_C = TRANSCODER_DSI_1, /* legacy DSI */
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I915_MAX_TRANSCODERS
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};
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/*
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* Per-pipe plane identifier.
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* I915_MAX_PLANES in the enum below is the maximum (across all platforms)
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* number of planes per CRTC. Not all platforms really have this many planes,
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* which means some arrays of size I915_MAX_PLANES may have unused entries
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* between the topmost sprite plane and the cursor plane.
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*
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* This is expected to be passed to various register macros
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* (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
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*/
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enum plane_id {
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/* skl+ universal plane names */
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PLANE_1,
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PLANE_2,
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PLANE_3,
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PLANE_4,
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PLANE_5,
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PLANE_6,
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PLANE_7,
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PLANE_CURSOR,
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I915_MAX_PLANES,
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/* pre-skl plane names */
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PLANE_PRIMARY = PLANE_1,
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PLANE_SPRITE0,
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PLANE_SPRITE1,
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};
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enum port {
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PORT_NONE = -1,
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PORT_A = 0,
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PORT_B,
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PORT_C,
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PORT_D,
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PORT_E,
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PORT_F,
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PORT_G,
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PORT_H,
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PORT_I,
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/* tgl+ */
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PORT_TC1 = PORT_D,
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PORT_TC2,
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PORT_TC3,
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PORT_TC4,
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PORT_TC5,
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PORT_TC6,
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/* XE_LPD repositions D/E offsets and bitfields */
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PORT_D_XELPD = PORT_TC5,
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PORT_E_XELPD,
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I915_MAX_PORTS
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};
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enum hpd_pin {
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HPD_NONE = 0,
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HPD_TV = HPD_NONE, /* TV is known to be unreliable */
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HPD_CRT,
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HPD_SDVO_B,
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HPD_SDVO_C,
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HPD_PORT_A,
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HPD_PORT_B,
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HPD_PORT_C,
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HPD_PORT_D,
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HPD_PORT_E,
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HPD_PORT_TC1,
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HPD_PORT_TC2,
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HPD_PORT_TC3,
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HPD_PORT_TC4,
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HPD_PORT_TC5,
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HPD_PORT_TC6,
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HPD_NUM_PINS
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};
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#endif /* __INTEL_DISPLAY_LIMITS_H__ */
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