f26b6af51d
Move all DPFC_CHICKEN programming into intel_fbc_program_workarounds(). We already have one thing programmed there, whereas the rest is strewn about in intel_display_wa_apply() and init_clock_gating(). Since we have a single place doing all the programming (and it's serialized by the crtc commits) there should be no danger of rmw races. Other FBC related workarounds also exist, but those require fiddling with other registers that may also get programmed from other places, so we'll need to think harder what to do with those. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240123090051.29818-2-ville.syrjala@linux.intel.com Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
40 lines
1,008 B
C
40 lines
1,008 B
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_reg.h"
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#include "intel_de.h"
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#include "intel_display_wa.h"
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static void gen11_display_wa_apply(struct drm_i915_private *i915)
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{
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/* Wa_14010594013 */
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intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);
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}
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static void xe_d_display_wa_apply(struct drm_i915_private *i915)
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{
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/* Wa_14013723622 */
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intel_de_rmw(i915, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);
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}
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static void adlp_display_wa_apply(struct drm_i915_private *i915)
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{
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/* Wa_22011091694:adlp */
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intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
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/* Bspec/49189 Initialize Sequence */
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intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
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}
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void intel_display_wa_apply(struct drm_i915_private *i915)
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{
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if (IS_ALDERLAKE_P(i915))
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adlp_display_wa_apply(i915);
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else if (DISPLAY_VER(i915) == 12)
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xe_d_display_wa_apply(i915);
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else if (DISPLAY_VER(i915) == 11)
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gen11_display_wa_apply(i915);
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}
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