018a7bdbb0
We need to inform PCODE of a desired ring frequencies so PCODE update
the memory frequencies to us. rps->min_freq and rps->max_freq are the
frequencies used in that request. However they were unset when SLPC was
enabled and PCODE never updated the memory freq.
v2 (as Suggested by Ashutosh): if SLPC is in use, let's pick the right
frequencies from the get_ia_constants instead of the fake init of
rps' min and max.
v3: don't forget the max <= min return
v4: Move all the freq conversion to intel_rps.c. And the max <= min
check to where it belongs.
v5: (Ashutosh) Fix old comment s/50 HZ/50 MHz and add a doc explaining
the "raw format"
Fixes: 7ba79a6715 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled")
Cc: <stable@vger.kernel.org> # v5.15+
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Tested-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220831214538.143950-1-rodrigo.vivi@intel.com
121 lines
3.8 KiB
C
121 lines
3.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef INTEL_RPS_H
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#define INTEL_RPS_H
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#include "intel_rps_types.h"
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#include "i915_reg_defs.h"
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struct i915_request;
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void intel_rps_init_early(struct intel_rps *rps);
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void intel_rps_init(struct intel_rps *rps);
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void intel_rps_sanitize(struct intel_rps *rps);
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void intel_rps_driver_register(struct intel_rps *rps);
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void intel_rps_driver_unregister(struct intel_rps *rps);
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void intel_rps_enable(struct intel_rps *rps);
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void intel_rps_disable(struct intel_rps *rps);
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void intel_rps_park(struct intel_rps *rps);
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void intel_rps_unpark(struct intel_rps *rps);
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void intel_rps_boost(struct i915_request *rq);
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void intel_rps_dec_waiters(struct intel_rps *rps);
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u32 intel_rps_get_boost_frequency(struct intel_rps *rps);
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int intel_rps_set_boost_frequency(struct intel_rps *rps, u32 freq);
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int intel_rps_set(struct intel_rps *rps, u8 val);
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void intel_rps_mark_interactive(struct intel_rps *rps, bool interactive);
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int intel_gpu_freq(struct intel_rps *rps, int val);
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int intel_freq_opcode(struct intel_rps *rps, int val);
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u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1);
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u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
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u32 intel_rps_get_requested_frequency(struct intel_rps *rps);
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u32 intel_rps_get_min_frequency(struct intel_rps *rps);
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u32 intel_rps_get_min_raw_freq(struct intel_rps *rps);
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int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val);
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u32 intel_rps_get_max_frequency(struct intel_rps *rps);
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u32 intel_rps_get_max_raw_freq(struct intel_rps *rps);
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int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val);
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u32 intel_rps_get_rp0_frequency(struct intel_rps *rps);
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u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
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u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
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u32 intel_rps_read_punit_req(struct intel_rps *rps);
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u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
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void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps);
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void intel_rps_raise_unslice(struct intel_rps *rps);
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void intel_rps_lower_unslice(struct intel_rps *rps);
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u32 intel_rps_read_throttle_reason(struct intel_rps *rps);
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bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);
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void gen5_rps_irq_handler(struct intel_rps *rps);
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void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
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void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
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static inline bool intel_rps_is_enabled(const struct intel_rps *rps)
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{
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return test_bit(INTEL_RPS_ENABLED, &rps->flags);
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}
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static inline void intel_rps_set_enabled(struct intel_rps *rps)
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{
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set_bit(INTEL_RPS_ENABLED, &rps->flags);
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}
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static inline void intel_rps_clear_enabled(struct intel_rps *rps)
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{
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clear_bit(INTEL_RPS_ENABLED, &rps->flags);
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}
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static inline bool intel_rps_is_active(const struct intel_rps *rps)
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{
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return test_bit(INTEL_RPS_ACTIVE, &rps->flags);
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}
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static inline void intel_rps_set_active(struct intel_rps *rps)
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{
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set_bit(INTEL_RPS_ACTIVE, &rps->flags);
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}
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static inline bool intel_rps_clear_active(struct intel_rps *rps)
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{
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return test_and_clear_bit(INTEL_RPS_ACTIVE, &rps->flags);
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}
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static inline bool intel_rps_has_interrupts(const struct intel_rps *rps)
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{
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return test_bit(INTEL_RPS_INTERRUPTS, &rps->flags);
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}
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static inline void intel_rps_set_interrupts(struct intel_rps *rps)
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{
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set_bit(INTEL_RPS_INTERRUPTS, &rps->flags);
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}
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static inline void intel_rps_clear_interrupts(struct intel_rps *rps)
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{
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clear_bit(INTEL_RPS_INTERRUPTS, &rps->flags);
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}
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static inline bool intel_rps_uses_timer(const struct intel_rps *rps)
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{
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return test_bit(INTEL_RPS_TIMER, &rps->flags);
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}
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static inline void intel_rps_set_timer(struct intel_rps *rps)
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{
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set_bit(INTEL_RPS_TIMER, &rps->flags);
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}
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static inline void intel_rps_clear_timer(struct intel_rps *rps)
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{
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clear_bit(INTEL_RPS_TIMER, &rps->flags);
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}
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#endif /* INTEL_RPS_H */
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