dd16ac404a
Actually it is a part of Conor's commitaae538cd03("riscv: fix detection of toolchain Zihintpause support"). It is looks like a merge issue. Samuel's commit0b1d60d6dd("riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y") do not base on Conor's commit and revert to __riscv_zihintpause. So this patch can fix it. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Fixes:3c349eacc5("Merge patch "riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y"") Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230802064215.31111-1-minda.chen@starfivetech.com Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
32 lines
686 B
C
32 lines
686 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __ASM_VDSO_PROCESSOR_H
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#define __ASM_VDSO_PROCESSOR_H
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#ifndef __ASSEMBLY__
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#include <asm/barrier.h>
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static inline void cpu_relax(void)
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{
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#ifdef __riscv_muldiv
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int dummy;
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/* In lieu of a halt instruction, induce a long-latency stall. */
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__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
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#endif
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#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
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/*
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* Reduce instruction retirement.
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* This assumes the PC changes.
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*/
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__asm__ __volatile__ ("pause");
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#else
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/* Encoding of the pause instruction */
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__asm__ __volatile__ (".4byte 0x100000F");
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#endif
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barrier();
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_VDSO_PROCESSOR_H */
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