88ef4c5bb3
[Why] Most of the time, a single display uses the ODM combine. When using multi-display, we use ODM combine only if it is necessary. These cases are not flexible enough for us, and we can improve them to take advantage of our hardware. We want to have more control over the ODM policy. [How] This commit add a new debug flag named enable_single_display_2to1_odm_policy to control the ODM policy and another flag named enable_dp_dig_pixel_rate_div_policy to fine control the ODM combine. This is possible by adding a new "pipe.dest" parameter that can be set to ODM 2:1 combined if we use a single display. For dynamic ODM combine, when using DP-DIG, DCN applies K2=2 settings for ODM combine. Note that this feature affects the following registers: - timing.pix_clk_100khz -> DP_VID_M, DP_VID_N - requested_pix_clk_100hz -> DP_DTOn_PHASE - OTGn_PIXEL_RATE_DIVK2 - DP_PIXEL_PER_CYCLE_PROCESSING_MODE - DIG_FIFO_OUTPUT_PIXEL_MODE - DP_VID_N_MUL Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
87 lines
2.9 KiB
C
87 lines
2.9 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_HWSS_DCN32_H__
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#define __DC_HWSS_DCN32_H__
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#include "hw_sequencer_private.h"
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struct dc;
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void dcn32_dsc_pg_control(
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struct dce_hwseq *hws,
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unsigned int dsc_inst,
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bool power_on);
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void dcn32_enable_power_gating_plane(
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struct dce_hwseq *hws,
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bool enable);
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void dcn32_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
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bool dcn32_apply_idle_power_optimizations(struct dc *dc, bool enable);
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void dcn32_cab_for_ss_control(struct dc *dc, bool enable);
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void dcn32_commit_subvp_config(struct dc *dc, struct dc_state *context);
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bool dcn32_set_mcm_luts(struct pipe_ctx *pipe_ctx,
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const struct dc_plane_state *plane_state);
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bool dcn32_set_input_transfer_func(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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const struct dc_plane_state *plane_state);
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bool dcn32_set_output_transfer_func(struct dc *dc,
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struct pipe_ctx *pipe_ctx,
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const struct dc_stream_state *stream);
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void dcn32_init_hw(struct dc *dc);
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void dcn32_program_mall_pipe_config(struct dc *dc, struct dc_state *context);
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void dcn32_update_mall_sel(struct dc *dc, struct dc_state *context);
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void dcn32_subvp_update_force_pstate(struct dc *dc, struct dc_state *context);
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void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
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unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsigned int *k1_div, unsigned int *k2_div);
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void dcn32_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
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void dcn32_subvp_pipe_control_lock(struct dc *dc,
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struct dc_state *context,
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bool lock,
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bool should_lock_all_pipes,
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struct pipe_ctx *top_pipe_to_program,
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bool subvp_prev_use);
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void dcn32_unblank_stream(struct pipe_ctx *pipe_ctx,
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struct dc_link_settings *link_settings);
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bool dcn32_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
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#endif /* __DC_HWSS_DCN32_H__ */
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