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minor optimization

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This commit is contained in:
Jaklyy 2024-12-27 16:48:49 -05:00
parent 459c088345
commit 4d4f374e70
2 changed files with 2 additions and 3 deletions
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1
src/ARM.cpp
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@ -1513,7 +1513,6 @@ void ARMv5::ForceInterlock_2()
void ARMv5::QueueFunction(void (ARMv5::*QueueEntry)(void)) void ARMv5::QueueFunction(void (ARMv5::*QueueEntry)(void))
{ {
if (QueueEntry == nullptr) return;
if ((NDS.ARM9Timestamp >= NDS.ARM9Target) || (MRTrack.Type != MainRAMType::Null)) if ((NDS.ARM9Timestamp >= NDS.ARM9Target) || (MRTrack.Type != MainRAMType::Null))
FuncQueue[FuncQueueFill++] = QueueEntry; FuncQueue[FuncQueueFill++] = QueueEntry;
else else

4
src/CP15.cpp
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@ -443,7 +443,7 @@ bool ARMv5::ICacheLookup(const u32 addr)
Store = false; Store = false;
RetVal = cacheLine[(addr & (ICACHE_LINELENGTH -1)) / 4]; RetVal = cacheLine[(addr & (ICACHE_LINELENGTH -1)) / 4];
QueueFunction(DelayedQueue); if (DelayedQueue != nullptr) QueueFunction(DelayedQueue);
return true; return true;
} }
} }
@ -556,7 +556,7 @@ void ARMv5::ICacheLookup_2()
} }
Store = false; Store = false;
DataRegion = Mem9_Null; DataRegion = Mem9_Null;
QueueFunction(DelayedQueue); if (DelayedQueue != nullptr) QueueFunction(DelayedQueue);
} }
void ARMv5::ICacheInvalidateByAddr(const u32 addr) void ARMv5::ICacheInvalidateByAddr(const u32 addr)