MIN_HUGEPTE_SHIFT hasn't been used since commit d1837cba5d
("powerpc/mm: Cleanup initialization of hugepages on powerpc")
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
UART3 device is not really needed for enabling audio block on TM2.
Enabling it made it working by enabling some common parent clocks,
what is now handled by improved exynos5433 clocks driver. Thus the UART3
device node can be safely disabled. The assigned-clocks entries are
however still needed, so move them under the respective CMU node.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Without this patch the clkout clock is orphaned and sound doesn't
work properly.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
a board specific item.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Audio PLL and oscillator clocks are proper parent clocks for AUD CMU.
They are not visible as such on first glance on Exynos5433 SoC docs,
but they are needed for this CMU to operate properly.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This patch corrects FSYS CMU parent clocks specified in clock controller
node to let improved Exynos5433 clocks driver to control proper clocks
on FSYS<->TOP CMU boundary.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts. The
GIC requires shared interrupts to be edge rising or level high. Platform
declares support for both. Set all interrupts type to level high, as this
works fine - tested on Exynos5433-based TM2 board.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
All places which used the TSC_RELIABLE to skip the delayed calibration
have been converted to use the TSC_KNOWN_FREQ flag.
Make the immeditate clocksource registration, which skips the long term
calibration, solely depend on TSC_KNOWN_FREQ.
The TSC_RELIABLE now merily removes the requirement for a watchdog
clocksource.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Bin Gao <bin.gao@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
reliable and the frequency is known (provided by HW).
On these platforms PIT/HPET is generally not available so calibration won't
work at all and there is no other clocksource to act as a watchdog for the
TSC, so we have no other choice than to trust it.
Set both X86_FEATURE_TSC_KNOWN_FREQ and X86_FEATURE_TSC_RELIABLE flags to
make sure the calibration is skipped and no watchdog is required.
Signed-off-by: Bin Gao <bin.gao@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1479241644-234277-5-git-send-email-bin.gao@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
On Intel GOLDMONT Atom SoC TSC is the only available clocksource, so there
is no way to do software calibration or have a watchdog clocksource for it.
Software calibration is already disabled via the TSC_KNOWN_FREQ flag, but
the watchdog requirement still persists, so such systems cannot switch to
high resolution/nohz mode.
Mark it reliable, so it becomes usable. Hardware teams confirmed that this
is safe on that SoC.
Signed-off-by: Bin Gao <bin.gao@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1479241644-234277-4-git-send-email-bin.gao@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
CPUs/SoCs with CPUID leaf 0x15 come with a known frequency and will report
the frequency to software via CPUID instruction. This hardware provided
frequency is the "real" frequency of TSC.
Set the X86_FEATURE_TSC_KNOWN_FREQ flag for such systems to skip the
software calibration process.
A 24 hours test on one of the CPUID 0x15 capable platforms was
conducted. PIT calibrated frequency resulted in more than 3 seconds drift
whereas the CPUID determined frequency showed less than 0.5 second
drift.
Signed-off-by: Bin Gao <bin.gao@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1479241644-234277-3-git-send-email-bin.gao@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The X86_FEATURE_TSC_RELIABLE flag in Linux kernel implies both reliable
(at runtime) and trustable (at calibration). But reliable running and
trustable calibration independent of each other.
Add a new flag X86_FEATURE_TSC_KNOWN_FREQ, which denotes that the frequency
is known (via MSR/CPUID). This flag is only meant to skip the long term
calibration on systems which have a known frequency.
Add X86_FEATURE_TSC_KNOWN_FREQ to the skip the delayed calibration and
leave X86_FEATURE_TSC_RELIABLE in place.
After converting the existing users of X86_FEATURE_TSC_RELIABLE to use
either both flags or just X86_FEATURE_TSC_KNOWN_FREQ we can seperate the
functionality.
Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Bin Gao <bin.gao@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1479241644-234277-2-git-send-email-bin.gao@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
KVM calls kvm_pmu_set_counter_event_type() when PMCCFILTR is configured.
But this function can't deals with PMCCFILTR correctly because the evtCount
bits of PMCCFILTR, which is reserved 0, conflits with the SW_INCR event
type of other PMXEVTYPER<n> registers. To fix it, when eventsel == 0, this
function shouldn't return immediately; instead it needs to check further
if select_idx is ARMV8_PMU_CYCLE_IDX.
Another issue is that KVM shouldn't copy the eventsel bits of PMCCFILTER
blindly to attr.config. Instead it ought to convert the request to the
"cpu cycle" event type (i.e. 0x11).
To support this patch and to prevent duplicated definitions, a limited
set of ARMv8 perf event types were relocated from perf_event.c to
asm/perf_event.h.
Cc: stable@vger.kernel.org # 4.6+
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Wei Huang <wei@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
We're missing the handling code for the cycle counter accessed
from a 32bit guest, leading to unexpected results.
Cc: stable@vger.kernel.org # 4.6+
Signed-off-by: Wei Huang <wei@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This patch enables perf core PMU support for the new AMD family-17h processors.
In family-17h, there is no PMC-event constraint. All events, irrespective of
the type, can be measured using any of the six generic performance counters.
Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
Acked-by: Borislav Petkov <bp@suse.de>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/1479399306-13375-1-git-send-email-Janakarajan.Natarajan@amd.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
ARCH_MEDIATEK is enabled
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJYJdNtAAoJELQ5Ylss8dND7QYQAKWFXsk/2sYV4UUDQ3ZxeSd+
DjyXJpxuRaNafYhBbRY1J93+GfhqCl4s4l3qSTSiYUOHOAuNx5p2jMNAurwJFArH
LC4PeiluoLUnRsAe3I0urYz7KKKAUUVr+J5izgQbKyuBSnn+fToATbJrVI/kS27F
1KRM99Hgt6ZYUWRb0PC5cKW8yGgsQa2Jhakocr9JLRVJsjfrZvceGcuaKRstDTYi
wocFxoJ8pk1YUCtIX6iVPY3i6MKYZY6aupTC8CwO8+GfSpq0KoPB0UWEBtN0BxRH
rHRn+Bu2k6/jmROlIPjtxgvcO7unVvZWrO/tO7TICocCa8TpJ19EJMNeiqvm5auM
z1m81i1LvfgMcU9FPDtzGp+UlVe1fFNwwLTMJkQjAFRodiBDXqqsEE7OZY1eT0hM
zGdo2JXuDzeo8cuWfADSKK3tM/TjIN/J7cEs3/OqkA3+pQtUJi+LS6CdyShmUBHD
oETxMN78loT3tcsSfXUMkD/PGp1/hDuAGe1uW8pj+/i8ZZb6kA5kqA+X6NK3ZBwX
80j2jS6IaMY3tpvMjukz5CVzf3sfztS0x1Bse61YYYmjDeVe9phxZ/NNwz1YTZbm
7e1GFGaNYlvFf701g1uGiWDq/YwkCrM1B4/9t/dmzD0vRppectt4DPnqAcoezv78
XMph+g3Ebz7Mplbe/Itd
=pzZG
-----END PGP SIGNATURE-----
Merge tag 'v4.9-next-kconfig' of https://github.com/mbgg/linux-mediatek into next/soc
- clean up mach-mediatek Makefile as kbuild only descends into the folder if
ARCH_MEDIATEK is enabled
* tag 'v4.9-next-kconfig' of https://github.com/mbgg/linux-mediatek:
ARM: mediatek: clean up mach-mediatek/Makefile
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add clocks for auxadc on mt8173-evb
- Add nodes needed by clock controller for mt2701
- Use clocks from the clock controller for the uart of mt2701
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJYJdcrAAoJELQ5Ylss8dNDoJcP/2q1LuStbojWMWxFKexQBCIk
8VEPzY8fyEckshbmgnz36qqp2MnecTLjb1ETesFIEGZWbEBnoAJC9hyIg6fFVZQi
mFZC8/0I7uvaFZHa+a3fQZb3tCmLMcWbAaGvA0p28kNRKnRhTMVHhLa7Z0WmMrG+
lQLlBBTP/xHErOakFJagkFIWYmmmMReS7x+X/tnVPienxkwODjpLYJQLL1wVmoqV
lpSj/nSRRDg8CeeG8/x+Odtr77L56glDMwwieXVpBe2sd+CpRk3QSTTcuYLkUp46
JBBKrr7TLLD6KEw6FgPjvjWDR3TH7S2wkbZVJN4B+8tmdEhpQhnle2MpJ6TYLKQb
ENwZ9JP70UD8o6mWb5e/g9R82WxUq1KDpdlU71OeBsnqfJRn1sge8bsO6+qs4+6Z
JapDW+Zwsewp9VZS12k4VdsCsYR0MZgX6XXj/NOOseJOMUXBFAoHj7vaC5Gj0UIT
VFKndrzWjIaVbaLHA/2KyVvOpJsEVTwSURyEko6XnTRLg+E85SSx+r6Bp3rlSlCV
Javet8M9YTLhPa1IeFMvf/1V4C4poX5tE4tvCiSZC1Wvxto5FSEgeGarq59Pgyi3
UWnxao8FHBHi3NU8khTI+rnIYtw5WxkEpqU5UUTYMUwsQ3x83VnU0WzpCSKQSNdD
Od24wmc/rrNKeU098abr
=wFjD
-----END PGP SIGNATURE-----
Merge tag 'v4.9-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt
- Add bindings for mtk-scpsys for mt2701
- Add clocks for auxadc on mt8173-evb
- Add nodes needed by clock controller for mt2701
- Use clocks from the clock controller for the uart of mt2701
* tag 'v4.9-next-dts' of https://github.com/mbgg/linux-mediatek:
arm: dts: mt2701: Use real clock for UARTs
arm: dts: mt2701: Add clock controller device nodes
arm64: dts: mt8173: Fix auxadc node
soc: mediatek: Add MT2701 power dt-bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
a fix for wrong i2c registers on rk3368 a new nvmem cell and
power-domain on rk3399 as well as moving mmc frequency
properties to the more generic max-frequency one.
-----BEGIN PGP SIGNATURE-----
iQEtBAABCAAXBQJYJzRqEBxoZWlrb0BzbnRlY2guZGUACgkQ86Z5yZzRHYE8HAgA
hFPUM6OmYsP81xJ8B8NscxZXi0r5ZTp14ouF5cREPF5mwXghrE5ZEGC/+xQJ/X4p
WSSGglNEJV5Ofs869wYDU3yZwNRzwkK7bGY+Mzq8eySYzkfZR2VZUf5ZStsLfUS1
j6Gr7jr2gwFtpjlwLmaUj8O4i/I3FfTiDLobqdpXoeoRcisLXS4/xDxEC1143TDR
ctylpGFEW/LXC1L4kTyLUZ6688654IC5qZBp4yHLIgb+qfd8k+CEjEyxtCzGpAQJ
sLQnsjjer4C3MqgOSDAjyguKpePCz0VIoE8wct136sQh20isbgWuhQjQ9+QzAaE+
/N+j0d87kaHUdPa097wQkg==
=LC5U
-----END PGP SIGNATURE-----
Merge tag 'v4.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
64bit devicetree changes including the px5 evaluation board
a fix for wrong i2c registers on rk3368 a new nvmem cell and
power-domain on rk3399 as well as moving mmc frequency
properties to the more generic max-frequency one.
* tag 'v4.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"
arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399
arm64: dts: rockchip: add sdmmc support for px5-evb
arm64: dts: rockchip: Add more properties for emmc on px5-evb
arm64: dts: rockchip: Add PX5 Evaluation board
arm64: dts: rockchip: add powerdomain for typec on rk3399
arm64: dts: rockchip: fix i2c resource error of rk3368
Signed-off-by: Olof Johansson <olof@lixom.net>
inclusion, missing unit names for memory nodes, various frequency
optimizations allowing for better performance on rk3066, the usage of
pin constants to bridge between the two numbering schemes used (gpio
controllers using 0-31 and pins being labeled A0-A7,..., D0-D7)
and UHS/HS modes for the mmc controllers on the popmetal board.
Two new boards, the PX3-based evaluation board, with the PX3 being an
industrial variant of the rk3188 soc and the Rikomagic MK808 board
based around the rk3066 are also added.
-----BEGIN PGP SIGNATURE-----
iQEtBAABCAAXBQJYJzNfEBxoZWlrb0BzbnRlY2guZGUACgkQ86Z5yZzRHYGsQQf/
WWYA4/oR4pT8HMns5coctc2zOyNU8KYmaeRl7TViUna+HA6/m2SGMqomTFV2AK0v
Ha3M6A35dDUGJNmAbEB5oolGOwHh82gZKYxYIQiNX+zCxeb5JxKCXWSqAjC9Ndwu
h600H1K/Qb26OzaVE/ICtlveduN+9BWrlzNseHsm99Z93FNsRLN0Z8s2Mn3jra6P
2Pf1sJkOPuh47i/Y/gTDVcFSf6Srb4SM/26fiZjrRa8LaaO/0I2Ku34ne9FygGzi
0GBHWh2SILM297MZMcrCDoJvTTqLT05tUrX1PDGmdunqP8vnsOAgvL9291G8d4sw
PbYE3onlyoxHmeOSffAe5g==
=AXPK
-----END PGP SIGNATURE-----
Merge tag 'v4.10-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
32bit devicetree changes for Rockchip including removal of skeleton.dtsi
inclusion, missing unit names for memory nodes, various frequency
optimizations allowing for better performance on rk3066, the usage of
pin constants to bridge between the two numbering schemes used (gpio
controllers using 0-31 and pins being labeled A0-A7,..., D0-D7)
and UHS/HS modes for the mmc controllers on the popmetal board.
Two new boards, the PX3-based evaluation board, with the PX3 being an
industrial variant of the rk3188 soc and the Rikomagic MK808 board
based around the rk3066 are also added.
* tag 'v4.10-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (21 commits)
ARM: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"
ARM: dts: rockchip: Set sdmmc frequency at boot time for rk3066a
ARM: dts: rockchip: use pin constants to describe gpios on Popmetal-RK3288
include: dt-bindings: Add GPIO pin index definition for rockchip pinctrl
ARM: dts: rockchip: Add rk3066 MK808 board
devicetree: Add vendor prefix for Rikomagic
ARM: dts: rockchip: initialize rk3066 PLL clock rate
clk: rockchip: Add binding ids for cpu and peri clocks on rk3066
ARM: dts: rockchip: enable HS200/DDR52 mode for emmc on rk3288-popmetal
ARM: dts: rockchip: Support UHS mode for SD card on PopMetal-RK3288 board
ARM: dts: rockchip: remove always-on and boot-on from vcc_sd for px3-evb
ARM: dts: rockchip: update compatible strings for Rockchip efuse
ARM: dts: rockchip: add rockchip PX3 Evaluation board
ARM: dts: rockchip: Add missing unit name to memory nodes in rk3xxx boards
ARM: dts: rockchip: Add missing unit name to memory nodes in rk3288 boards
ARM: dts: rockchip: Add missing unit name to memory nodes in rk322x boards
ARM: dts: rockchip: Add missing unit name to memory nodes in rk3036 boards
ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3xxx.dtsi
ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk3288.dtsi
ARM: dts: rockchip: Remove skeleton.dtsi inclusion in rk322x.dtsi
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add specific compatible strings for variants of Cyclone5 boards
- Add QSPI node on Arria10
- Enable QSPI on Arria5 and Arria10 devkit, and Cyclone5 SoCKit
- Add NAND controller node on Cyclone5
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYJiljAAoJEBmUBAuBoyj0ySQP/Arwy1gmyK/mQ9/W/WSPdm0h
aqcRuSjMTlmL+R6myWTpNyDIysbCROYzJFapK4YiGQProIWvgR9Z/kjuDDsSqHmI
IV01euJvPFMklwL1MwhhlDrBPJtSkOZtL912C03NBQSfCc6rcmfWTBmGOOJtlSkd
V1nxL+uOu0bGRxsrRy9z4iGXy7DfeqyIIIZ0PHuUqbHaEX0HldID1vX5vS0ymuv8
EwZXvf/nPrqO/pY+sOJ3QTb4sMcUwwOqcliXJ3d/U/qWz5OS9NEl4ROiKOjyhPX4
hUkr7Hymftd/33fkDYaiVyHZaCz/7QZQ6G+69VHLu0zKMiTMc2afNTJ6EDJJ+uS2
PIk+6AWtSGucFqytmfcqLUWgVHJUhXDJmuvGs7ibYAuw+jnAz/gr8H9l7QClm+V1
Z5LYApPDDC/khRwlvh8Ce356WxeL5n1zbw0Mq6Avz9TrC7bw2vGmw37UWA9TlA5T
elsLjmjdAEo0UNajGUy/oSrDmR3iZAgtraxSM07QDzPYg3zKxJpSiM9eWtMFTo/i
RVkkxYEXLP5skbW1Mh5KGaDGecwhfYQwV58WvXpu+hA+Lv1MKo+QuENA2H2vf46J
AGe/77KFVjrjeqoYbN4dVVZ+uhVccsO7VGE3lZ7MBKE/fEb2Ici1JfaJb7ABc4Rj
liho+hmnwVbWQeQc+Je7
=clFU
-----END PGP SIGNATURE-----
Merge tag 'socfpga_dts_for_v4.10_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS update for v4.10, part 2
- Add specific compatible strings for variants of Cyclone5 boards
- Add QSPI node on Arria10
- Enable QSPI on Arria5 and Arria10 devkit, and Cyclone5 SoCKit
- Add NAND controller node on Cyclone5
* tag 'socfpga_dts_for_v4.10_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: add nand controller nodes
ARM: dts: socfpga: Enable QSPI on the Arria5 devkit
ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit
ARM: dts: socfpga: Enable QSPI in Arria10 devkit
ARM: dts: socfpga: Add QSPI node for the Arria10
ARM: dts: socfpga: enable qspi on the Cyclone5 devkit
ARM: dts: socfpga: add specific compatible strings for boards
Signed-off-by: Olof Johansson <olof@lixom.net>
* 'sti-defconfig-for-4.10-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
ARM: multi_v7_defconfig: Remove ST_THERMAL_SYSCFG Kconfig symbol
Signed-off-by: Olof Johansson <olof@lixom.net>
The EBI lookup is not longer in use: this has been moved to the
NAND chip driver. The syscon node is better accessed indirectly
using the regmap like the NAND chip driver does, so let's use
the syscon to set the modem control signals RTS/CTS through the
dedicated syscon register.
We also migrate the decoder status "SC_DEC" register that
enumerate the logic modules using syscon.
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This cycle is covering :
- some clock fixes common with sa1100 architecture
- the consequence of the pxa_camera conversion to v4l2
- a small irq related fix for pxa25x device-tree only
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYIkw2AAoJEAP2et0duMsSAVMP/1nQWA24IXAFMEVBroGHz1r/
/RXS3eJ5sfGxVcvCMPTPiE18+jqGHtNgnZH2sFkwUqByTq5SkSZOS13q2gN6iUBs
M2zSqYS6FKQvEdzMzqOq5acyRR02fyrvn4SoaUBNUUzqJ93G7ITJjLnUm4EJ1RdU
rQ76MuHr/QB7q7L2OJtHwgoZt+CmxpioCRu+yW2UEhFNaJ6zRVrPyKtQNLzze7UB
BSgS8pKR1a8lMRwkt8ciw40Pz5YDKOI7ZYgEwms50fu0GliFTt0RrbE7H5Gm9ur4
mDR7m9puhLssAFIXIQc7mSMNI88CsUFhRmqeKfBOtWQ/1IKXSCZiAQrUY+DRH+fo
xAOJlzF88V7nKpnkmN+fvZeOnUusPS2Avree0dZT8VyNa2FvdvBXOJmdZXAA81FG
YIwpVV3ZLud5rT3eHWzpCInDUbjw0wBrDYcdHenJTmdtAb5oRVJtWlWmZuk3f3iG
q9ILDAcVoWwI1orozbCcXS98hE74EPdUtkMzBnXCBYaplqsw2aAjbX5Usn30YEZz
SkE2bMh0yyv2J3yUNUgFWgDYsbgT8zRLOvUoy9g6OlisL3ZOT4QLghRzbAiW7bXG
UaK6ezzvK/oTABIS5gaWgRxR9oM2xNCST1CBBLX8g9o9NNj60AxSfVfh/i+iHp1B
Y03pa/bFqOWeeK1shPmD
=1WrE
-----END PGP SIGNATURE-----
Merge tag 'pxa-for-4.10' of https://github.com/rjarzmik/linux into next/soc
This is the pxa changes for v4.10 cycle.
This cycle is covering :
- some clock fixes common with sa1100 architecture
- the consequence of the pxa_camera conversion to v4l2
- a small irq related fix for pxa25x device-tree only
* tag 'pxa-for-4.10' of https://github.com/rjarzmik/linux:
ARM: pxa: fix pxa25x interrupt init
ARM: pxa: remove duplicated include from spitz.c
ARM: pxa: em-x270: use the new pxa_camera platform_data
ARM: pxa: ezx: use the new pxa_camera platform_data
ARM: pxa: mioa701: use the new pxa_camera platform_data
ARM: pxa: pxa_cplds: honor probe deferral
ARM: sa11x0/pxa: get rid of get_clock_tick_rate
watchdog: sa11x0/pxa: get rid of get_clock_tick_rate
ARM: sa11x0/pxa: acquire timer rate from the clock rate
clk: pxa25x: OSTIMER0 clocks from the main oscillator
Signed-off-by: Olof Johansson <olof@lixom.net>
On POWER9 DD1, when we do a local TLB invalidate we also need to explicitly
invalidate the ERAT.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
SoC along with two boards. A lot of Samsung people contributed into this
but the final work and commits were done by Chanwoo Choi.
This means that for v4.10 we got:
1. Exynos5433 DTSI.
2. Two boards: TM2 and TM2E. These are (almost fully) working mobile phones.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYIhaFAAoJEME3ZuaGi4PXu+0P/jN29SCAeg/9e/0LR0IB3/Zo
gCW4lRtunv0q3DzC6r5Wai0fZ/HgNi/3FUxAwVhS3D1+NdXYb9Dk5FL4v3Fqzsb1
ozbig+MC+imzIF281E3UFgSA38wn3er8xosFxeqYLqtlPT6UOv+wg6yuv2s6oYxN
4zS1SARsnp2pHCvLjCBM5LxO5+dx10NpUr+jEAw65yQbElq2iHAKgwro4KQPP/Bn
TU4Nx/yOiR7L/6IvgIN8zO/k/v8KyfRO/HM9yw4/ZLMO4AyX+/MhrBngHjELtxP6
CymvAlpJC9+FumWsMh5BiG7Jx7W0rlg1askyohff+fx7rCm8K6A+oLNE+RBex17W
vs+gsOCgHMPSdft/9eNkXd1U3c8fpZU59KW/8WFu6WSa2J0IFWmouYfwTYj80Xgk
NBd05IiY4X+UQ3+Jyl4CC7lttxfcizFNstx3HI/x+vYgZQTFrUONIxjVYm2pYYUk
tITYFev06qTVg21VVJhC0CZydDJzYf6jKhh6oqDz2TK1M2gpaGVbyWgMfNtZDWqR
/2Kb058Tf6q1fLG0O9EipQgQoiMLAVFMlNi8COZxYYFIXHI7WBF8pa6ybO1FbVIO
eDDJ80I6EjkcM3hm92jtNRYg86JQ4RDOq55vVzR9oxiaVmo3ecvWaIRFURR+OIw7
2bITXNAL7h5HNX6mx9Bx
=zbqq
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Finally, I am really pleased to announce adding support for Exynos5433 ARMv8
SoC along with two boards. A lot of Samsung people contributed into this
but the final work and commits were done by Chanwoo Choi.
This means that for v4.10 we got:
1. Exynos5433 DTSI.
2. Two boards: TM2 and TM2E. These are (almost fully) working mobile phones.
* tag 'samsung-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board
arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Add TOPEET itop core and Elite boards, based on Exynos4412.
2. Remove the Exynos4415 DTSI. We did not have any mainlined boards
using it. I am also not aware of any popular out-of-tree boards using it.
3. Add Snoop Control Unit node for Exynos4.
4. Minor cleanups.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYIhWlAAoJEME3ZuaGi4PXB5UP+QGT9d61jwD9uX1fe5v6OZkg
Cwy8HxFBeYXge8T4brCW0t48G6fARFHyVwZwJU/AA/nsDuvolaoZYJ8Ovp0gD4eH
Qoa2K9xd1wtzBHkasJk8CSpDNm48Nr1sgwt1k6H/qmOy90eBbVekIUHES+73K5DJ
8RaT3F/lAMOXztkb8RddoNt4GTNA/2ikdnGdvkvd4+cjGMvdkmUhBcY+28m7n9u8
r6Xir9rG5RWgrtZHh6Y6vZ0gnZaM27DjCl/MxmZjpGwwKjn0zm7AlMxLP6C+26rr
duSkuJZq7rL4vVOk7FlqDkmG4LZXwT+C4ZEryTZ7KMuCqWVP3dSzF4Flw4x8Cif3
cFiVuRHSiaIcq0aE1c6PNKg8N7+pqJxtRKu4sK/ce1vr5cADsZY/0sWdlZAdDJCQ
nm9U9XYXPiiRhaZFaa3slwd0gFqNd1zL/MjKKWGBfEk8PBydyy/F6YjDwbfyURTb
0tWCfgcLvPg0v2xw8pbsaA7vn4/PIjHD9YqraEFBJXUouZJpC+uU+5EyHiM9Rxil
vEvvRKjmTN5vBDR913p3G+XA6L5wOts8sgjl0HZiM+6lsMkcZ4xD8xHO3kpvZwL3
VXOWLjD0hzwo7L/Nw2ucEFF/2ToggxJC0Fnbxn0i8lU6tOnjkOp/xa4Y/Xo4UMTW
+6o++VlUs7k6kg1+kY8F
=qzwE
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Samsung DeviceTree update for v4.10:
1. Add TOPEET itop core and Elite boards, based on Exynos4412.
2. Remove the Exynos4415 DTSI. We did not have any mainlined boards
using it. I am also not aware of any popular out-of-tree boards using it.
3. Add Snoop Control Unit node for Exynos4.
4. Minor cleanups.
* tag 'samsung-dt-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Add SCU device node to exynos4.dtsi
ARM: dts: exynos: Remove exynos4415.dtsi
ARM: dts: exynos: Document eMMC/SD/SDIO devices in Snow and Peach boards
ARM: dts: exynos: Add TOPEET itop elite based board
ARM: dts: exynos: Add TOPEET itop core board SCP package version
ARM: dts: exynos: Add entries for sound support on Odroid-XU board
ARM: dts: exynos: Remove "simple-bus" compatible from fimc-is node
Signed-off-by: Olof Johansson <olof@lixom.net>
This includes a single functional change:
* set default parent clock for PWM1 & PWM2.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.14 (GNU/Linux)
iQIcBAABAgAGBQJYIcwQAAoJEJw94nR8/maC8t8QALZZmPEUuT6EUTGOP/3pZcws
GrXqajDjK4U3ot0cJkmmQ07VVNYilz1zpl2DiRmSKepSyhrG64dP9G5thYBamPom
nbkzlh3U02rjjyEgvidzbd+RisAMU5JJzIUAXROaghmhoC+SF87xFnttEU4PCRTg
iqLNJfp/6FmnRH1kccT4KwzAQhNjzcQYxqc1FY8DekRl1etHZLSHdqc5I6j2a4qO
BNKSEbv+xSbWqu0pMm5NFSwqkxTgSW7CgCOiezhHd2x3sLpKztXrZ0Y9S2Sis1rC
VfTEQ/FBhCvnyUF1B/Qjmz9iOM3WMrQyHBE5y5rqoVS4rf9E/8BDk0mSLmq7Keeu
ABZzlo6qa8wez1iAXhcHww6WDT4X3wRxxerZELADhU5orubch7R5hWJzL3wUp5N0
Zsxs5nhJjCAIPx5rI8vVz12EFu1XMpbc8cGX1Ah6nD5eVLE3YiMjQ+w8cJ+LI5bU
YTx4Co0CuyJItp2GUOzeXzTBzN/0vz1TZN4csLd5r6OVfSFXW0tG9CwYrnT8R1mA
E4DISdwWbbn3aAN/19g2Z0PwQzAl8QlQb2VWz16zzs4Ob0vl+jjU5PD70br17XiS
8CPKci0POBwRpx9K9j/uny5SWfmBpldvtlvicHCtmSeniuKkewtQhjJOZwgVCygQ
2dVGfgpXVYY1DjLNvLtf
=9l30
-----END PGP SIGNATURE-----
Merge tag 'lpc32xx-dt-v4.10' of https://github.com/sylemieux/linux-lpc32xx into next/dt
NXP LPC32xx ARM SoC device tree updates for v4.10
This includes a single functional change:
* set default parent clock for PWM1 & PWM2.
* tag 'lpc32xx-dt-v4.10' of https://github.com/sylemieux/linux-lpc32xx:
ARM: dts: lpc32xx: set default parent clock for pwm1 & pwm2
Signed-off-by: Olof Johansson <olof@lixom.net>
- Switch CPU enable-method from spin-table to PSCI
- Add OPP tables to support generic cpufreq driver
- Misc fixes
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYHfLxAAoJED2LAQed4NsGwnIP/3hE5jd52BkIf+LnM5muoiXd
A8FcqOQgj6zix6lrmAwQEGp+ociUiMYpQXgj8B5K1UwPKVRYjwvc1EuRQriI1btF
Kp8IIQnepLK2nRLliHl3w55bO7pdxx53rqeoF8HXF6FvkTMS1JycXI0pkZp8VkDQ
rDQ1LqCxBWtdTccOQgIUF615YysxpbrHZEbg7fYGtDmeEcu1e1c5VAnj0xgefWiY
C94iPba3HYKPQkn+6ueQR2M2VinNvl6V+m9FgmqcoQG5jDTyCM52DMD2h0RJMI9i
NsqxRfQAZc5B4ReyuFSDEKHwbqRwCx2o6LMWuyqCx2deRcHRS0hy6DiEnnaKheeC
Fqr4jnQwlE9lqXiCAklz1wNfO7bDdbWIfokRfDYxvBAQIQPbi2FUkDTYWqjoEU+8
VT6ZuPGYIjzDaZEMyVqN0PHj5mp4eQ4oBPDhyXrWU3d06Ky3I6yKMoQ43/inj1RC
BlA/OlsDr/uo2oYReqZGTSIGNYEAGoAqalV9paNDZxaIizzUHdRxoO97at7oHTHH
5HOCB3XP62cWFoE3t1yEoJBn6z/IrxCzTa8UkM+j/IMWT1xsoi3389u+5OOVgN7Y
oPi1pgdi82b6aD9QW4BG/RN0Pr+xTywPqU6omd14lKTlCxZfCOjLGrn2p0myg3GC
wbe4n2uoIL9AAnuYSfDg
=K2GC
-----END PGP SIGNATURE-----
Merge tag 'uniphier-dt64-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64
UniPhier ARM64 SoC DT updates for v4.10
- Switch CPU enable-method from spin-table to PSCI
- Add OPP tables to support generic cpufreq driver
- Misc fixes
* tag 'uniphier-dt64-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
arm64: dts: uniphier: make compatible of syscon nodes SoC-specific
arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC
arm64: dts: uniphier: increase register region size of sysctrl node
arm64: dts: uniphier: switch over to PSCI enable method
Signed-off-by: Olof Johansson <olof@lixom.net>
-----BEGIN PGP SIGNATURE-----
iQEcBAABAgAGBQJYFQwAAAoJEHm+PkMAQRiGr8YH/0urDFZm/RFu752rSawF7iVM
nx9Ck03YkRiMRZfdzPARbHJts7lhLG1rvsT50VQNMK1sVv0BXcrnJnDu49xV+dLj
DqXWvYGtdTCpAd34Am37pX/rrRl11vdJgS2VgprmbytkM8FD0xEe+aDKxnnmuALo
bggYDhMrJik3/UXG0zVfefKZJFLNAJiZv9AgWgkCR+bo861bu3UFn47tN1jGXOOl
QyFl5t7ggesojA5Q1U9hTrk1gS9Ia9it3Elyzfqb66lUdyf001I1nbUA/hNYyDXD
HU9dj3agvVXjvnDjyDR4/k86FA+EEEwSgk5CBTCVe30dLKnojFyb7FWZg72utg4=
=CHER
-----END PGP SIGNATURE-----
Merge tag 'v4.9-rc3' into next/dt64
Linux 4.9-rc3
* tag 'v4.9-rc3': (292 commits)
Linux 4.9-rc3
x86/smpboot: Init apic mapping before usage
ACPICA: Dispatcher: Fix interpreter locking around acpi_ev_initialize_region()
ACPICA: Dispatcher: Fix an unbalanced lock exit path in acpi_ds_auto_serialize_method()
ACPICA: Dispatcher: Fix order issue of method termination
ARC: module: print pretty section names
ARC: module: elide loop to save reference to .eh_frame
ARC: mm: retire ARC_DBG_TLB_MISS_COUNT...
ARC: build: retire old toggles
ARC: boot log: refactor cpu name/release printing
ARC: boot log: remove awkward space comma from MMU line
ARC: boot log: don't assume SWAPE instruction support
ARC: boot log: refactor printing abt features not captured in BCRs
ARCv2: boot log: print IOC exists as well as enabled status
ubifs: Fix regression in ubifs_readdir()
ubi: fastmap: Fix add_vol() return value test in ubi_attach_fastmap()
MAINTAINERS: Add entry for genwqe driver
VMCI: Doorbell create and destroy fixes
GenWQE: Fix bad page access during abort of resource allocation
vme: vme_get_size potentially returning incorrect value on failure
...
- Add OPP tables to support generic cpufreq driver
- Use more clocks/resets properties
- Misc fixes and cleanups
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYHfI6AAoJED2LAQed4NsGJr8P/iz2m4XuefXZj8GAuIScD1D3
CWSbsr9qG0w77AT+tae4yND9G5QSI6qHWZMmCWsv7GLnjKXzOzjRs0nlfflhOFaC
JrZAJrrPfpIuqITMgSPkljQ1uwW5hpJ0oS49y2LI6r2vwfTII/TezgVJ3ix43i0r
Ngx9/wX9sQWZBJYi54hsVMgNv3JzN3LXdYjGMDvLBCNLwo437m/yLF6z2ApzGj03
kEozI7jiw61jwdu9nPnvfsjxTADiIdW8114+ldzK5jGIgU7IvLIDIqa6QSbkIM0W
KnzFXOlyMofd7Gkyj0BZd4GGdrsWgK2MbXjSZA3XiwrU81G28E+2ANaQKiaod+kO
5tRgBf7pWfKS+21laQmKjxqTAtDVw3fjwkF8anJ5e482lB4r6T/DWh6vIc27grtP
N1eJ7WkgrErOhVZVNZ6AqvMLsZdDkHS9R1ZCk3rwCSptX0raJhtScqWqTFH7erWa
MFjT+8znHDF4fXX+i+fxWPMWoyJvZYIAevr0wtPpp+VbBl1GyAjAt5sntorFBXSy
35l4TgI11PCbTI6DCc/uV9CihJjZP2UGo1YC92SAIuvUqArfvsHby/yVjQlcsnzC
BAJZn1dnItkgzOb7np1vbl3YYRRJcN8eGkanSZ+DNaerhGKnk/KKzxUj09RfEUDp
51MOA2r2+w+SLUHurn1a
=DdcH
-----END PGP SIGNATURE-----
Merge tag 'uniphier-dt-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt
UniPhier ARM SoC DT updates for v4.10
- Add OPP tables to support generic cpufreq driver
- Use more clocks/resets properties
- Misc fixes and cleanups
* tag 'uniphier-dt-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
ARM: dts: uniphier: make compatible of syscon nodes SoC-specific
ARM: dts: uniphier: add clocks/resets to EHCI nodes of sLD3 SoC
ARM: dts: uniphier: remove redundant serial fifo-size properties
ARM: dts: uniphier: make 32bit SoC DTSI linear
ARM: dts: uniphier: add CPU clocks and OPP table for PXs2 SoC
ARM: dts: uniphier: add CPU clocks and OPP table for Pro5 SoC
ARM: dts: uniphier: increase register region size of sysctrl node
Signed-off-by: Olof Johansson <olof@lixom.net>
-----BEGIN PGP SIGNATURE-----
iQEcBAABAgAGBQJYFQwAAAoJEHm+PkMAQRiGr8YH/0urDFZm/RFu752rSawF7iVM
nx9Ck03YkRiMRZfdzPARbHJts7lhLG1rvsT50VQNMK1sVv0BXcrnJnDu49xV+dLj
DqXWvYGtdTCpAd34Am37pX/rrRl11vdJgS2VgprmbytkM8FD0xEe+aDKxnnmuALo
bggYDhMrJik3/UXG0zVfefKZJFLNAJiZv9AgWgkCR+bo861bu3UFn47tN1jGXOOl
QyFl5t7ggesojA5Q1U9hTrk1gS9Ia9it3Elyzfqb66lUdyf001I1nbUA/hNYyDXD
HU9dj3agvVXjvnDjyDR4/k86FA+EEEwSgk5CBTCVe30dLKnojFyb7FWZg72utg4=
=CHER
-----END PGP SIGNATURE-----
Merge tag 'v4.9-rc3' into next/dt
Linux 4.9-rc3
* tag 'v4.9-rc3': (292 commits)
Linux 4.9-rc3
x86/smpboot: Init apic mapping before usage
ACPICA: Dispatcher: Fix interpreter locking around acpi_ev_initialize_region()
ACPICA: Dispatcher: Fix an unbalanced lock exit path in acpi_ds_auto_serialize_method()
ACPICA: Dispatcher: Fix order issue of method termination
ARC: module: print pretty section names
ARC: module: elide loop to save reference to .eh_frame
ARC: mm: retire ARC_DBG_TLB_MISS_COUNT...
ARC: build: retire old toggles
ARC: boot log: refactor cpu name/release printing
ARC: boot log: remove awkward space comma from MMU line
ARC: boot log: don't assume SWAPE instruction support
ARC: boot log: refactor printing abt features not captured in BCRs
ARCv2: boot log: print IOC exists as well as enabled status
ubifs: Fix regression in ubifs_readdir()
ubi: fastmap: Fix add_vol() return value test in ubi_attach_fastmap()
MAINTAINERS: Add entry for genwqe driver
VMCI: Doorbell create and destroy fixes
GenWQE: Fix bad page access during abort of resource allocation
vme: vme_get_size potentially returning incorrect value on failure
...
Enhancements:
* Basic support for r8a7743 SoC; only SoC code so far
* Select errata 798181 for SoCs with CA15 cores
Clean-up:
* Consolidate R8A7743 and R8A779[234] machine definitions
Documentation:
* Add Marzen, Gose and Alt board part numbers to DT bindings
* Document SK-RZG1M board
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYHFSAAAoJENfPZGlqN0++i1gQAJvDzERhzjIl8ukWmnnVflIk
EtlT3PaoFtmstecrvMY5W8Hm7ViRUlBGbBDrE+c7WH4IHkEVbFTUef6nzAhXmSp6
ZgIOx3J1dYz1uWMCi5lBU6vZirut7VvyqWfIlMceSsq2WMS5TobM/rORvh4N0yQ1
MuhsxIuuuwJe0neMAs0lFeKFUoWm7RxFen6G6vXZWVg9INxKSKGKvh8+8IbhWP2H
WjMTUYASneLmZ5nIlyL8LTauOczsJitgHgYtoCCUMDFCcDKMth6HiMvZztny5sTs
Sk+SH/MKDo9fZWXWxHh0mS/bFIbdiY4/BfK0S2LlRo8MQMS0d3pKPIvD4gRT7Wyq
2JTuf4kuehI9+VEY0NNZH1HJnsFGN7ZB2C99eOkcvVsm324yhxy9MgxioyBYEgsY
ckr9/nbxvkYGI326AN4pvE6JF9oqnRdQiHQrRHg5sIuL2hpusALWlOeQnnnrKGQE
Xo+F9+DfhFTLosxqjq6abCwJ8t97uake0+ZRFUiJpjAHjc5se9qIN9njmanTCUhd
UwMHVgTs5zYLPCGjmbY+jw8NwLp5UWHTgfOewUA0399mcj/KRo06uB8pUYkVEVZz
s5FUnsOAhE7A2aNfAJWu4ecKIf5rvnE+ErIW/nYRp/sbTc9+zZkEVSAiMGQFlXcu
BOS+An3C04D6m1CY+tOv
=CqVV
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Renesas ARM Based SoC Updates for v4.10
Enhancements:
* Basic support for r8a7743 SoC; only SoC code so far
* Select errata 798181 for SoCs with CA15 cores
Clean-up:
* Consolidate R8A7743 and R8A779[234] machine definitions
Documentation:
* Add Marzen, Gose and Alt board part numbers to DT bindings
* Document SK-RZG1M board
* tag 'renesas-soc-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7779/marzen: Add board part number to DT bindings
ARM: shmobile: select errata 798181 for SoCs with CA15 cores
ARM: shmobile: Consolidate R8A7743 and R8A779[234] machine definitions
ARM: shmobile: r8a7793/gose: Add board part number to DT bindings
ARM: shmobile: r8a7794/alt: Add board part number to DT bindings
ARM: shmobile: document SK-RZG1M board
ARM: shmobile: r8a7743: basic SoC support
ARM: shmobile: only call rcar_gen2_clocks_init() if present
ARM: shmobile: Sort Kconfig selections
Signed-off-by: Olof Johansson <olof@lixom.net>
Clean-Ups and Corrections:
* Removed Z clock from r8a7794 SoC; it is not present in hardware
* Use generic pinctrl properties in SDHI nodes in gose board
* Correct W=1 dtc warnings on r8a7794 SoC
* Correct DU reg property on r8a7779 SoC
* Correct SCIFB reg properties to cover all registers
Enhancements:
* Configure pinmuxing for the DU0 input clock on the Marzen board
* Enable VIN 0 - 2 on r8a7793 SoC
* Enable HDMI input on Koelsch and Lager boards
* Enable SDHI1 on rskrza1 board
* Add MMCIF nodes to r7s72100 SoC
* Add MSIOF clocks to r8a7792 SoC
* Enable UHS for SDHI 0 & 1 on koelsch and alt boards
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYHFcMAAoJENfPZGlqN0++0YQQAKxHY52/hFqQAwUnfnFvOT0z
r3lb+MxTvLCi3xf1mM0JlnrughuvHAsQV0zv6DVo8eU9lKefSw9p/3/ROmfk1qU4
HR2pYE/1lAbDpnUBQEIO19XXerlrQQoN6bgAoGdHo+U4w+v4P3kG0RCqcIjelSPt
w9IUW9E9Tf24ZtS9Rn2N58JTOcvpPOP8TYvP8TL6Jp5eyngiWNcj0rOwKeiAmYd+
OsRhQ2FJjzdwYdQFdTSf3R5XeiUhg8HuCKiOLTIn/2o3AfVPxtC3p4b9NxCArvOv
+Y1um0y2VWClPTeDpbBC9whFx0hvqDF+rftiu1hZfr5vRGR0FYjEu7z2bvWAvIOT
qhN+BCBIfhsV1TDxqAmdaKSaBlxFLk+Z4LAMtvKrzVKf0f2XZQ7NoycIOoqmh57T
ARdcAwYRiPZvw3UUZKMqbL6U5rhlW9JJmnNC3EQfluR3R/SmGi2ZGdmqlLlfbKjp
U28OuzaSIP7Iou/8KmLHRUQvuBacaBB9fqDn6gDpgEVTSZTDOpvt0r1t0ovFC+F7
q/9loxKxva+I+rE1lAA7ejZ2VXb5d3AUY1Sfsw+aw0fv8q6rfU+HEM5/ppEPijDQ
YRsp4tRH17/lM9Go4VVH2Txl/ZK5tX/trXNJPFToG2/fJc5EWvCug6pF+p6QKIuf
BnqbAZFe9DWRBXpyLb/A
=Tkdc
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
Renesas ARM Based SoC DT Updates for v4.10
Clean-Ups and Corrections:
* Removed Z clock from r8a7794 SoC; it is not present in hardware
* Use generic pinctrl properties in SDHI nodes in gose board
* Correct W=1 dtc warnings on r8a7794 SoC
* Correct DU reg property on r8a7779 SoC
* Correct SCIFB reg properties to cover all registers
Enhancements:
* Configure pinmuxing for the DU0 input clock on the Marzen board
* Enable VIN 0 - 2 on r8a7793 SoC
* Enable HDMI input on Koelsch and Lager boards
* Enable SDHI1 on rskrza1 board
* Add MMCIF nodes to r7s72100 SoC
* Add MSIOF clocks to r8a7792 SoC
* Enable UHS for SDHI 0 & 1 on koelsch and alt boards
* tag 'renesas-dt-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (29 commits)
ARM: dts: r8a7794: remove Z clock
ARM: dts: r8a7779: marzen: Configure pinmuxing for the DU0 input clock
ARM: dts: sh73a0: Remove skeleton.dtsi inclusion
ARM: dts: r8a7740: Remove skeleton.dtsi inclusion
ARM: dts: r8a7779: Remove skeleton.dtsi inclusion
ARM: dts: r8a7778: Remove skeleton.dtsi inclusion
ARM: dts: emev2: Remove skeleton.dtsi inclusion
ARM: dts: r8a7779: Fix DU reg property
ARM: dts: r8a7793: Enable VIN0-VIN2
ARM: dts: koelsch: add HDMI input
ARM: dts: lager: Add entries for VIN HDMI input support
ARM: dts: rskrza1: add sdhi1 DT support
ARM: dts: r7s72100: add sdhi to device tree
ARM: dts: r8a7794: Fix W=1 dtc warnings
ARM: dts: gose: use generic pinctrl properties in SDHI nodes
ARM: dts: r7s72100: add sdhi clock to device tree
ARM: dts: r7s72100: add mmcif to device tree
ARM: dts: r8a7792: add MSIOF support
ARM: dts: r8a7792: add MSIOF clocks
ARM: dts: wheat: add DU support
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Add blue-and-red-wiring -property to LCDC node. Also adds comments on
how to get support 24 bit RGB mode. After this patch am335x-boneblack
support RGB565, BGR888, and XBGR8888 color formats. See details in
Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt.
The BBB has straight color wiring from am335x to tda19988, however the
tda19988 can be configured to cross the blue and red wires. The
comments show how to do that with video-ports property of tda19988
node and how to tell LCDC that blue and red wires are crossed, with
blue-and-red-wiring LCDC node property. This changes supported color
formats from 16 bit RGB and 24 bit BGR to 16 bit BGR and 24 bit RGB.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
A fix to reintroduce missing pinmux options that turned out not to be
optional.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJYK3mGAAoJEBx+YmzsjxAg2nEQAK/mc4R4yram78qXD5B+tbji
o04PuC2xvST0xI7N4fnNxueZQOYoqKEvbUlGa32kQ4Zs20qCrnRntlfjjNvs+UQc
O9EOTJnH1T+sABY+LOq3rcoK8zswl7ka+dsQ3STaL+OFVfox+Bw2IjCZ1KBOLjgU
4joOeuOTrmSTS5i6IxvGPmGZBb5hbq9TaYsQyIKUozaLjDGgDgZ1GKjJhN9LdjM5
n7K8Bf87YQhuxKgQv2H3rxseooe95IVmfc8zv+CnLSrC63oJwpiAemVuaPKOq7dt
gTxkYIBBtHMwY/OHpXRI0FNxuhaPUn8Nxo9QxTij9aH44lfZr2RS/0f/KHIe2KrM
Nh8mUMTotgSfdmD5OrShgJV28B6MxzJMhUisi+GGglR0N4GNeXZ5dtNOgY35Rmjw
geJNPjnL7ALkXcrLPxGyPttcw8p/wtSgDnbOINWZ0aJ7NfTgqCsi4uYkOJSm4NII
unthkLr/y5uwWMkPNoGtoqGOF0kMTcXy5gf/S45mdKzU2c8dKi6POph7kVeVxC1F
OBIQ+s2H0E4D6rOz9g7R7lwO/tFVltXz1lhvQ+CebM5/NH1vjVuKDe0+SrvDfQBm
6IYzepW3tVjJTWJr09xUfzwtkm5ii6lEvChllnmrInhpgDCnKv9qDgbnJCnLlUYs
D7JrBkNV+976JqdOlX5l
=WBs5
-----END PGP SIGNATURE-----
Merge tag 'sunxi-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into fixes
Allwinner fixes for 4.9
A fix to reintroduce missing pinmux options that turned out not to be
optional.
* tag 'sunxi-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: dts: sun8i: fix the pinmux for UART1
Signed-off-by: Olof Johansson <olof@lixom.net>
